Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders

Pass transistor logic (PTL) is a circuit design technique wherein transistors are used as switches. The reconfigurable mesh (RM) is a model that exploits the power of PTLs signal switching, by enabling flexible bus connections in a grid of processing elements containing switches. RM algorithms have theoretical results proving that [Formula: see text] can speed up computations significantly. However, the RM assumes that the latency of broadcasting a signal through [Formula: see text] switches (bus length) is 1. This is an unrealistic assumption preventing physical realizations of the RM. We propose the restricted-RM (RRM) wherein the bus lengths are restricted to [Formula: see text], [Formula: see text]. We show that counting the number of 1-bits in an input of [Formula: see text] bits can be done in [Formula: see text] steps for [Formula: see text] by an [Formula: see text] RRM. An almost matching lower bound is presented, using a technique which adds to the few existing lower-bound techniques in this area. Finally, the algorithm was directly coded over an FPGA, outperforming an optimal tree of adders. This work presents an alternative way of counting, which is fundamental for summing, beating regular Boolean circuits for large numbers, where summing a vast amount of numbers is the basis of any accelerator in embedded systems such as neural-nets and streaming. a

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Analytical derivation of the optimal traffic signal timing: Minimizing delay variability and spillback probability for undersaturated intersections

Transportation Research Part B Methodological ◽

10.1016/j.trb.2018.11.004 ◽

2019 ◽

Vol 119 ◽

pp. 45-68 ◽

Cited By ~ 7

Author(s):

Reza Mohajerpoor ◽

Meead Saberi ◽

Mohsen Ramezani

Keyword(s):

Traffic Signal ◽

Signal Timing ◽

Analytical Derivation ◽

Delay Variability ◽

Traffic Signal Timing

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Digital compressor structure in neural network implementation using complex complementary pass-transistor logic (C/sup 2/PL)

Proceedings of 1994 37th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.1994.519282 ◽

2002 ◽

Author(s):

D. Zhang ◽

M. Kamel ◽

M.I. Elmasry

Keyword(s):

Neural Network ◽

Pass Transistor ◽

Pass Transistor Logic

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A pass transistor design methodology for 256 Mbit DRAM and beyond

Proceedings of 1994 VLSI Technology Symposium ◽

10.1109/vlsit.1994.324419 ◽

2002 ◽

Cited By ~ 3

Author(s):

A. Chatterjee ◽

J. Liu ◽

P.K. Mozumder ◽

M. Rodder ◽

I.-C. Chen

Keyword(s):

Design Methodology ◽

Pass Transistor

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