A Low Power Sense Amplifier Flip-Flop With Balanced Rise/Fall Delay

2006 ◽  
Author(s):  
Rubil Ahmadi
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Sense Amplifier

Single‐ended structure sense‐amplifier‐based flip‐flop for low‐power systems

2015 ◽  
Vol 51 (1) ◽  
pp. 20-21 ◽  
Author(s):  
Jin‐Fa Lin ◽  
Yin‐Tsung Hwang ◽  
Chen‐Syuan Wong ◽  
Ming‐Hwa Sheu
Keyword(s):  
Power Systems ◽  
Low Power ◽  
Flip Flop ◽  
Sense Amplifier

Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design

2019 ◽  
Vol E102.C (11) ◽  
pp. 833-838
Author(s):  
Po-Yu KUO ◽  
Chia-Hsin HSIEH ◽  
Jin-Fa LIN ◽  
Ming-Hwa SHEU ◽  
Yi-Ting HUNG
Keyword(s):  
Low Power ◽  
Low Complexity ◽  
Flip Flop ◽  
Sense Amplifier

SINUSOIDAL CLOCKED SENSE-AMPLIFIER-BASED ENERGY RECOVERY FLIP-FLOPS

2014 ◽  
Vol 23 (05) ◽  
pp. 1450066
Author(s):  
JITENDRA KANUNGO ◽  
S. DASGUPTA
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Energy Recovery ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Sense Amplifier ◽  
Simulation Based ◽  
Digital Circuit Design

Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed flip-flop operating with energy recovery single phase sinusoidal clock shows better performance. The proposed flip-flop also reduces the leakage current and glitch.

scholarly journals Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

2021 ◽  
Author(s):  
komal swami ◽  
Ritu Sharma
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Low Energy ◽  
Clock Gating ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Transition Control ◽  
Sense Amplifier ◽  
Gating Mechanism ◽  
Power Delay Product

Abstract Energy conservation and delay minimization are the two major goals while designing ultra-low-power digital integrated circuits at lower technology nodes. Here, silicon based carbon nanotube field effect transistor (CNTFET) has been explored as a novel material for future electronics design applications (EDA). In this paper, two energy-efficient switching activity minimization techniques have been applied with proposed designs. First technique detects the completion of sensing stage operation known as transition completion detection (TCD) technique. TC signal generated from NAND operation of complementary outputs of sensing stage which minimizes glitches in the complementary outputs of the latch stage. Another clock gating mechanism applied at the latch stage to smoothen the output waveforms Q and . The proposed and existing designs simulated using 32nm CMOS and 32nm CNTFET technology, indicating that the CNTFET based design reduces power by 45% and 36% respectively in comparison with conventional CMOS. Proposed Low Power Sense Amplifier Flip Flop with transition control detection (TCD-LPSAFF) and Ultra Low Energy Sense Amplifier Flip Flop (ULESAFF) give optimum power delay product (PDP) which is 35.7x10-18 J and 29.6x10-18 J respectively. Also, the effect of process variation has been analyzed at specified corners (FF, TT and SS) in the temperature range of -40º C to 120º C. The performance of all designs has been validated by functionality testing with variation in diameter, number of tubes and pitch respectively.

Data-dependant sense-amplifier flip-flop for low power applications

2010 ◽  
Author(s):  
Farshad Moradi ◽  
Charles Augustine ◽  
Ashish Goel ◽  
Georgeos Karakonstantis ◽  
Tuan Vu Cao ◽  
...  
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Sense Amplifier

scholarly journals A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 802
Author(s):  
Heng You ◽  
Jia Yuan ◽  
Weidi Tang ◽  
Zenghui Yu ◽  
Shushan Qiao
Keyword(s):  
Low Power ◽  
High Speed ◽  
Input Data ◽  
Low Voltage ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Low Voltage Operation ◽  
Amplifier Stage ◽  
Simulation Results ◽  
Power Delay Product

In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm2 (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.

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