scholarly journals A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 802
Author(s):  
Heng You ◽  
Jia Yuan ◽  
Weidi Tang ◽  
Zenghui Yu ◽  
Shushan Qiao
Keyword(s):  
Low Power ◽  
High Speed ◽  
Input Data ◽  
Low Voltage ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Low Voltage Operation ◽  
Amplifier Stage ◽  
Simulation Results ◽  
Power Delay Product

In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm2 (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

Design of low power and high speed implicit pulse flip-flop and its application

2018 ◽  
Vol 7 (3) ◽  
pp. 1893 ◽  
Author(s):  
Kuruvilla John ◽  
Vinod Kumar R S ◽  
Kumar S S
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Product Performance ◽  
Power Performance ◽  
Flip Flop ◽  
Power Efficient ◽  
Pass Transistor ◽  
Simulation Results ◽  
Power Delay Product ◽  
Pmos Transistor

In this paper, a new power efficient and high speed pulsed-triggered flip-flop in implicit style with conditional pulse enhancement and signal feed-through (CPESFTFF) is proposed. This novel architecture is presented for the pulse-triggered D-FF in the CMOS 90-nm technology. Two important features are embedded in this flip-flop architecture. Firstly, a conditional enhancement in width and height of the triggering pulses by using an additional pMOS transistor in the structure is done. Secondly, a modified signal feed-through mechanism which directly samples the input to output by using an nMOS pass transistor is introduced. The proposed design achieves better speed and power performance by successfully solving the longest discharging path problem. The simulation results show that the proposed architecture has improvement in terms of power consumption, D-to-Q delay, and Power Delay Product Performance (PDP) in comparison with other conventional P-FF architectures. A 3-bit up counter is also implemented using proposed P-FF.  

MODIFIED CONDITIONAL-PRECHARGE SENSE-AMPLIFIER-BASED FLIP-FLOP WITH IMPROVED SPEED

2007 ◽  
Vol 16 (02) ◽  
pp. 199-210 ◽  
Author(s):  
FEI QIAO ◽  
HUAZHONG YANG ◽  
DINGLI WEI ◽  
HUI WANG
Keyword(s):  
Noise Immunity ◽  
Power Reduction ◽  
Reduction Ratio ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Simulation Results ◽  
Output Delay ◽  
Power Delay Product

A modified version of conditional-precharge sense-amplifier-based flip-flop (mCP-SAFF) is proposed. By using the differential clocked CMOS (C2MOS) latch with one shared output holder and the conditional-precharge modules to simplify the sense-amplifier latch, the mCP-SAFF can achieve a much shorter input to output delay (D-to-Q delay) and more symmetrical rising/falling delays than those of the original conditional-precharge sense-amplifier-based flip-flops (CP-SAFF). Post-layout simulation results show that the mCP-SAFF, compared with the widely used conventional DFF, does not suffer neither timing nor area penalties and have achieved up to 34% of power reduction ratio and 33% of power-delay-product (PDP) reduction ratio, respectively. And the mCP-SAFF is comparable to the prevailing DFFs with regard to noise immunity performance.

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

2015 ◽  
Vol 19 ◽  
pp. 19-36 ◽  
Author(s):  
P.A. Gowri Sankar ◽  
G. Sathiyabama
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Field Effect ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Flash Adc ◽  
Simulation Results

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

scholarly journals Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

2021 ◽  
Author(s):  
komal swami ◽  
Ritu Sharma
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Low Energy ◽  
Clock Gating ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Transition Control ◽  
Sense Amplifier ◽  
Gating Mechanism ◽  
Power Delay Product

Abstract Energy conservation and delay minimization are the two major goals while designing ultra-low-power digital integrated circuits at lower technology nodes. Here, silicon based carbon nanotube field effect transistor (CNTFET) has been explored as a novel material for future electronics design applications (EDA). In this paper, two energy-efficient switching activity minimization techniques have been applied with proposed designs. First technique detects the completion of sensing stage operation known as transition completion detection (TCD) technique. TC signal generated from NAND operation of complementary outputs of sensing stage which minimizes glitches in the complementary outputs of the latch stage. Another clock gating mechanism applied at the latch stage to smoothen the output waveforms Q and . The proposed and existing designs simulated using 32nm CMOS and 32nm CNTFET technology, indicating that the CNTFET based design reduces power by 45% and 36% respectively in comparison with conventional CMOS. Proposed Low Power Sense Amplifier Flip Flop with transition control detection (TCD-LPSAFF) and Ultra Low Energy Sense Amplifier Flip Flop (ULESAFF) give optimum power delay product (PDP) which is 35.7x10-18 J and 29.6x10-18 J respectively. Also, the effect of process variation has been analyzed at specified corners (FF, TT and SS) in the temperature range of -40º C to 120º C. The performance of all designs has been validated by functionality testing with variation in diameter, number of tubes and pitch respectively.

scholarly journals A Modified Signal Feed-Through Pulsed Flip- Flop for Low Power Applications

2017 ◽  
Vol 63 (3) ◽  
pp. 241-246 ◽  
Author(s):  
Ehsan Panahifar ◽  
Alireza Hassanzadeh
Keyword(s):  
Low Power ◽  
Input Data ◽  
Power Reduction ◽  
Leakage Power ◽  
Flip Flop ◽  
Dynamic Power ◽  
Pass Transistor ◽  
Power Delay Product ◽  
Hspice Simulation

AbstractIn this paper a modified signal feed-through pulsed flip-flop has been presented for low power applications. Signal feed-through flip-flop uses a pass transistor to feed input data directly to the output. Feed through transistor and feedback signals have been modified for delay, static and dynamic power reduction. HSPICE simulation shows 22% reduction in leakage power and 8% of dynamic power. Delay has been reduced by 14% using TSMC 90nm technology parameters. The proposed pulsed flip-flop has the lowest PDP (Power Delay Product) among other pulsed flip-flops discussed.

New Design of Scan Flip-Flop to Increase Speed and Reduce Power Consumption

2015 ◽  
Vol 24 (10) ◽  
pp. 1550159 ◽  
Author(s):  
Ramin Razmdideh ◽  
Ali Mahani ◽  
Mohsen Saneei
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Switching Activity ◽  
Flip Flop ◽  
Reduce Power Consumption ◽  
Controlled Switching ◽  
Simulation Results

In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented, in which short circuit current is controlled. Switching activity is decreased to reduce the consumed power of the scan flip-flop. Also, the total number of transistors through the path from input to the output is reduced and so the delay of the proposed scan flip-flop is decreased. Simulation results show 12% and 29% reduction in power consumption and delay of the proposed scan flip-flop, respectively. The results are given by comparison of our work with other scan flip-flops at 50% data switching activity.

AN ULTRA LOW-POWER CURRENT-MODE SENSE AMPLIFIER FOR SRAM APPLICATIONS

2005 ◽  
Vol 14 (05) ◽  
pp. 939-951 ◽  
Author(s):  
ZHI-HUI KONG ◽  
KIAT-SENG YEO ◽  
CHIP-HONG CHANG
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Power Efficient ◽  
Power Characteristics ◽  
Sense Amplifier ◽  
Micro Power ◽  
Power Delay Product

A novel micro-power current sense amplifier employing a cross-coupled current-mirror configuration is presented. The circuit is designed for low-voltage low-power SRAM applications. Its sensing speed is independent of the bit-line capacitances and is almost insensitive to the data-line capacitances. Extensive post-layout simulation results based on a 1.8 V/0.18 μm CMOS technology from Chartered Semiconductor Manufacturing Ltd. (CHRT) have verified that the new sense amplifier promises a much sought-after power-efficient advantage and a note-worthy power-delay product superiority over the conventional and recently reported sense amplifier circuits. These attributes of the proposed sense amplifier make it judiciously appropriate for use in the contemporary high-complexity regime, which incessantly craves for low-power characteristics.

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