Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing

2006 13th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2006.379631 ◽

2006 ◽

Cited By ~ 1

Author(s):

Bo Fu ◽

Paul Ampadu

Keyword(s):

Critical Path ◽

Leakage Power ◽

Cmos Circuits ◽

Power Minimization ◽

Nanoscale Cmos ◽

Transistor Sizing

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Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization

2007 44th ACM/IEEE Design Automation Conference ◽

10.1109/dac.2007.375129 ◽

2007 ◽

Author(s):

De-Shiuan Chiou ◽

Da-Cheng Juan ◽

Yu-Ting Chen ◽

Shih-Chieh Chang

Keyword(s):

Leakage Power ◽

Power Minimization ◽

Fine Grained ◽

Transistor Sizing

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Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2008.2001247 ◽

2009 ◽

Vol 17 (9) ◽

pp. 1330-1334 ◽

Cited By ~ 9

Author(s):

De-Shiuan Chiou ◽

Shih-Hsin Chen ◽

Shih-Chieh Chang

Keyword(s):

Leakage Power ◽

Power Minimization ◽

Transistor Sizing ◽

Charge Balancing

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Neural network based optimization of CMOS transistor sizing for leakage power minimization

2012 International Conference on Innovations in Information Technology (IIT) ◽

10.1109/innovations.2012.6207724 ◽

2012 ◽

Author(s):

Omar Banimelhem ◽

Rami Bani Hani

Keyword(s):

Neural Network ◽

Leakage Power ◽

Power Minimization ◽

Transistor Sizing ◽

Cmos Transistor

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Fine-grained sleep transistor sizing algorithm for leakage power minimization

2007 44th ACM/IEEE Design Automation Conference ◽

10.1145/1278480.1278502 ◽

2007 ◽

Cited By ~ 17

Author(s):

De-Shiuan Chiou ◽

Da-Cheng Juan ◽

Yu-Ting Chen ◽

Shih-Chieh Chang

Keyword(s):

Leakage Power ◽

Power Minimization ◽

Fine Grained ◽

Transistor Sizing

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Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2010.2046812 ◽

2010 ◽

Vol 29 (8) ◽

pp. 1285-1289 ◽

Cited By ~ 3

Author(s):

De-Shiuan Chiou ◽

Yu-Ting Chen ◽

Da-Cheng Juan ◽

Shih-Chieh Chang

Keyword(s):

Temporal Correlation ◽

Leakage Power ◽

Power Minimization ◽

Transistor Sizing

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On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits

2008 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2008.4542029 ◽

2008 ◽

Cited By ~ 2

Author(s):

A. Sathanur ◽

A. Calimera ◽

A. Pullini ◽

L. Benini ◽

A. Macii ◽

...

Keyword(s):

Leakage Power ◽

Cmos Circuits ◽

Power Gating ◽

Power Minimization ◽

Figures Of Merit ◽

Nanometer Cmos

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The epsilon-approximation to discrete VT assignment for leakage power minimization

Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09 ◽

10.1145/1687399.1687453 ◽

2009 ◽

Cited By ~ 2

Author(s):

Yujia Feng ◽

Shiyan Hu

Keyword(s):

Leakage Power ◽

Power Minimization

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