Practical works for on-line teaching design and test of digital circuits

2003 ◽  
Author(s):  
A. Jutman ◽  
R. Ubar ◽  
V. Hahanov ◽  
O. Skvortsova
Keyword(s):  
Digital Circuits ◽  
Teaching Design ◽  
On Line

A BDD-based approach to design power-aware on-line detectors for digital circuits

2010 ◽  
Author(s):  
Gopal Paul ◽  
Santosh Biswas ◽  
Chittaranjan Manda ◽  
Bhargab B. Bhattacharya
Keyword(s):  
Digital Circuits ◽  
On Line ◽  
Design Power

scholarly journals Parity Codes Used for On-Line Testing in FPGA

10.14311/788 ◽  
2005 ◽  
Vol 45 (6) ◽  
Author(s):  
P. Kubalík ◽  
H. Kubátová
Keyword(s):  
Error Detection ◽  
Digital Circuits ◽  
Fault Model ◽  
Concurrent Error Detection ◽  
Combinational Circuit ◽  
Safe Operation ◽  
On Line ◽  
Xilinx Fpga ◽  
Eda Tools

This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit must be detected and signalized at the time of its appearance and before further distribution of errors. Hence safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. Combinational circuit benchmarks have been used in this work in order to compute the quality of the proposed codes. The description of the benchmarks is based on equations and tables. All of our experimental results are obtained by XILINX FPGA implementation EDA tools. A possible TSC structure consisting of several TSC blocks is presented. 

On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models

2005 ◽  
Author(s):  
S. Biswas ◽  
P. Srikanth ◽  
R. Jha ◽  
S. Mukhopadhyay ◽  
A. Patra ◽  
...  
Keyword(s):  
Digital Circuits ◽  
Fault Models ◽  
Bridging Fault ◽  
On Line

Elitist Pool Evolutionary Algorithm for On-Line Evolution of Digital Circuits

2010 ◽  
Vol 33 (2) ◽  
pp. 365-372 ◽  
Author(s):  
Guo-Liang HE ◽  
Yuan-Xiang LI ◽  
Zhong-Zhi SHI
Keyword(s):  
Evolutionary Algorithm ◽  
Digital Circuits ◽  
On Line

Methodology for low power design of on-line testers for digital circuits

2008 ◽  
Vol 95 (8) ◽  
pp. 785-797 ◽  
Author(s):  
S. Biswas ◽  
G. Paul ◽  
S. Mukhopadhyay
Keyword(s):  
Low Power ◽  
Digital Circuits ◽  
Low Power Design ◽  
On Line
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