On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models

2005 ◽  
Author(s):  
S. Biswas ◽  
P. Srikanth ◽  
R. Jha ◽  
S. Mukhopadhyay ◽  
A. Patra ◽  
...  
Keyword(s):  
Digital Circuits ◽  
Fault Models ◽  
Bridging Fault ◽  
On Line

UNIFIED TECHNIQUE FOR ON-LINE TESTING OF DIGITAL CIRCUITS: DELAY AND STUCK-AT FAULT MODELS

2008 ◽  
Vol 17 (06) ◽  
pp. 1069-1089 ◽  
Author(s):  
S. BISWAS ◽  
S. MUKHOPADHYAY ◽  
A. PATRA ◽  
D. SARKAR
Keyword(s):  
Cell Count ◽  
Digital Circuits ◽  
Deep Submicron ◽  
Line Detection ◽  
Delay Faults ◽  
Fault Models ◽  
Bridging Faults ◽  
Area Overhead ◽  
Transition Faults ◽  
On Line

This work is concerned with the development of generic, nonintrusive, and flexible algorithms for the design of digital circuits with on-line testing (OLT) capability. Most of the works presented in the literature on OLT have used single stuck at (s - a) fault models. However, in the deep submicron technology, single s - a fault models may not capture more than a fraction of the real defects. To cater to the problem it is now advocated that additional fault models such as bridging faults, transition faults, delay faults, etc., are also used. The proposed technique is one of the first works that facilitates a unified scheme for on-line detection of delay faults and s - a faults with a high value of n for n-Detect tests. The technique can handle generic digital circuits with cell count as high as 15,000 and having the order of 2500 states. Results for the design of on-line detectors for various ISCAS89 benchmark circuits are provided. The results illustrate that with marginal increase in the area overhead, if compared to the ones with single s - a fault coverage only, the proposed scheme also provides coverage for the delay faults.

A BDD-based approach to design power-aware on-line detectors for digital circuits

2010 ◽  
Author(s):  
Gopal Paul ◽  
Santosh Biswas ◽  
Chittaranjan Manda ◽  
Bhargab B. Bhattacharya
Keyword(s):  
Digital Circuits ◽  
On Line ◽  
Design Power

Fault Models Usability Study for On-line Tested FPGA

2011 ◽  
Author(s):  
Jaroslav Borecky ◽  
Martin Kohlik ◽  
Pavel Kubalik ◽  
Hana Kub´tov´
Keyword(s):  
Usability Study ◽  
Fault Models ◽  
On Line

Fault Detection of Bridging Faults in Digital Circuits by Shared Binary Decision Diagram

2010 ◽  
Vol 439-440 ◽  
pp. 1235-1240
Author(s):  
Ling Chen ◽  
Zhong Liang Pan
Keyword(s):  
Digital Circuits ◽  
Binary Decision Diagram ◽  
Test Method ◽  
Bridging Faults ◽  
Binary Decision ◽  
Xor Operation ◽  
Bridging Fault ◽  
Multiple Primary ◽  
Test Vectors ◽  
Logic Functions

A new test generation method for the bridging faults in digital circuits is proposed in this paper, the method is based on shared binary decision diagram. The shared binary decision diagram can represent many logic functions simultaneously by sharing isomorphic subgraphs, it is used to represent the digital circuits with multiple primary outputs. The binary decision diagram is constructed respectively for the normal circuit and faulty circuit having a bridging fault. The test vectors of the bridging fault can be produced by a XOR operation of the two binary decision diagrams. The experimental results on a lot of benchmark circuits demonstrate that the test method proposed in this paper can get the test vectors of the bridging faults if the faults are testable.

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