Test pattern generator for hybrid testing of combinational circuits

2002 ◽  
Author(s):  
D. De Caro ◽  
N. Mazzocca ◽  
E. Napoli ◽  
G.P. Saggese ◽  
A.G.M. Strollo
Keyword(s):  
Test Pattern ◽  
Pattern Generator ◽  
Combinational Circuits ◽  
Hybrid Testing

scholarly journals Testability-Driven Layout of Combinational Circuits

VLSI Design ◽  
1998 ◽  
Vol 7 (4) ◽  
pp. 347-352
Author(s):  
C. P. Ravikumar ◽  
Nikhil Sharma
Keyword(s):  
Test Generation ◽  
Test Pattern ◽  
Pattern Generator ◽  
Test Vector ◽  
Combinational Circuits ◽  
Bridging Faults ◽  
Cpu Time ◽  
On Line ◽  
Placement Algorithm ◽  
Automatic Test Pattern Generator

The layout of a circuit can influence the probability of occurrence of faults. In this paper, we develop algorithms that can take advantage of this fact to reduce the chances of hard-to-detect (HTD) faults from occurring. We primarily focus on line bridge faults in this paper. We define a bridge fault f as an HTD fault if an automatic test pattern generator fails to generate a test vector for f in a reasonable amount of CPU-time. It is common practice to drop such HTD faults from consideration during test generation. The chip fault coverage achieved by a test set is poor if the fault set consists of many HTD faults. We can combat this problem by avoiding altogether, or by reducing the probability of, the occurrence of HTD faults. In this paper, we consider hard-to-detect bridging faults and show how module placement rules can be derived to reduce the probability of these faults. A genetic placement algorithm that optimizes area while respecting these rules is presented. The placement algorithm has been implemented for standard-cell layout style on a SUN/SPARC and tested against several sample circuits.

scholarly journals An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits

VLSI Design ◽  
1994 ◽  
Vol 2 (3) ◽  
pp. 199-207
Author(s):  
Hyung K. Lee ◽  
Dong S. Ha
Keyword(s):  
Processing Time ◽  
Test Pattern ◽  
Pattern Generator ◽  
Cmos Circuit ◽  
Combinational Circuits ◽  
Automatic Test ◽  
Set Size ◽  
Short Processing Time ◽  
Open Faults ◽  
Automatic Test Pattern Generator

In this paper, we describe a highly efficient automatic test pattern generator for stuck-open (SOP) faults, called SOPRANO, in CMOS combinational circuits. The key idea of SOPRANO is to convert a CMOS circuit into an equivalent gate level circuit and SOP faults into the equivalent stuck-at faults. Then SOPRANO derives test patterns for SOP faults using a gate level test pattern generator. Several techniques to reduce the test set size are introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANO achieves high SOP fault coverage and short processing time.

Dynamic Photon Emission on FinFET Devices Through Novel Scan Test Approaches

2019 ◽  
Author(s):  
Ranganathan Gopinath ◽  
Ravikumar Venkat Krishnan ◽  
Lua Winson ◽  
Phoa Angeline ◽  
Jin Jie
Keyword(s):  
Test Pattern ◽  
Photon Emission ◽  
Pattern Generator ◽  
Lower Probability ◽  
Automated Test Equipment ◽  
Use Patterns ◽  
Infra Red ◽  
Automatic Test Pattern Generator ◽  
Technology Nodes ◽  
Established Technique

Abstract Dynamic Photon Emission Microscopy (D-PEM) is an established technique for isolating short and open failures, where photons emitted by transistors are collected by sensitive infra-red detectors while the device under test is electrically exercised with automated test equipment (ATE). Common tests, such as scan, use patterns that are generated through Automatic Test Pattern Generator (ATPG) in compressed mode. When these patterns are looped for D-PEM, it results in indeterministic states within cells during the load or unload sequences, making interpretation of emission challenging. Moreover, photons are emitted with lower probability and lesser energies for smaller technology nodes such as the FinFET. In this paper, we will discuss executing scan tests in manners that can be used to bring out emission which did not show up in conventional test loops.

scholarly journals UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs

Integration ◽  
2016 ◽  
Vol 55 ◽  
pp. 85-97 ◽  
Author(s):  
Cinzia Bernardeschi ◽  
Luca Cassano ◽  
Andrea Domenici ◽  
Luca Sterpone
Keyword(s):  
Test Pattern ◽  
Pattern Generator
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