Handling High Speed Traffic Measurement Using Network Processors

2006 ◽  
Author(s):  
Ruan Donghua ◽  
Lin Chuang ◽  
Chen Zhen ◽  
Ni Jia ◽  
Peter D. Ungsunan
Keyword(s):  
High Speed ◽  
Network Processors ◽  
Traffic Measurement

Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units

2007 ◽  
Vol 31 (3) ◽  
pp. 188-199 ◽  
Author(s):  
K. Vlachos ◽  
T. Orphanoudakis ◽  
Y. Papaeftathiou ◽  
N. Nikolaou ◽  
D. Pnevmatikatos ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
High Speed ◽  
Packet Processing ◽  
Network Processors ◽  
High Speed Network ◽  
And Performance ◽  
Processing Engine

scholarly journals SAPTM: Towards High-Throughput Per-Flow Traffic Measurement with a Systolic Array-Like Architecture on FPGA

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1160 ◽  
Author(s):  
Qixuan Cheng ◽  
Xiaolei Zhao ◽  
Mei Wen ◽  
Junzhong Shen ◽  
Minjin Tang ◽  
...  
Keyword(s):  
High Throughput ◽  
Systolic Array ◽  
High Speed ◽  
Data Centers ◽  
Computational Cost ◽  
Space Utilization ◽  
Approximate Methods ◽  
Traffic Measurement ◽  
Network Bandwidth ◽  
High Space

Per-flow traffic measurement has emerged as a critical but challenging task in data centers in recent years in the face of massive network traffic. Many approximate methods have been proposed to resolve the existing resource-accuracy trade-off in per-flow traffic measurement, one of which is the sketch-based method. However, sketches are affected by their high computational cost and low throughput; moreover, their measurement accuracy is hard to guarantee under the conditions of changing network bandwidth or flow size distribution. Recently, FPGAplatforms have been widely deployed in data centers, as they demonstrate a good fit for high-speed network processing. In this work, we aim to address the problem of per-flow traffic measurement from a hardware architecture perspective. We thus design SAPTM, a pipelined systolic array-like architecture for high-throughput per-flow traffic measurement on FPGA. We adopt memory-friendly D-left hashing in the design of SAPTM, which guarantees high space utilization during flow insertion and eviction, successfully addressing the challenge of tracking a high-speed data stream under limited memory resources on FPGA. Evaluations on the Xilinx VCU118 platform with real-world benchmarks demonstrate that SAPTM possesses high space utilization. Comparisons with state-of-the-art sketch-based solutions show that SAPTM outperforms comparison methods in terms of throughput by a factor of 14.1x–70.5x without any accuracy loss.

An Efficient K-Persistent Spread Estimator for Traffic Measurement in High-Speed Networks

2020 ◽  
Vol 28 (4) ◽  
pp. 1463-1476
Author(s):  
He Huang ◽  
Yu-E Sun ◽  
Chaoyi Ma ◽  
Shigang Chen ◽  
You Zhou ◽  
...  
Keyword(s):  
High Speed ◽  
Traffic Measurement ◽  
High Speed Networks
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