scholarly journals SAPTM: Towards High-Throughput Per-Flow Traffic Measurement with a Systolic Array-Like Architecture on FPGA

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1160 ◽  
Author(s):  
Qixuan Cheng ◽  
Xiaolei Zhao ◽  
Mei Wen ◽  
Junzhong Shen ◽  
Minjin Tang ◽  
...  
Keyword(s):  
High Throughput ◽  
Systolic Array ◽  
High Speed ◽  
Data Centers ◽  
Computational Cost ◽  
Space Utilization ◽  
Approximate Methods ◽  
Traffic Measurement ◽  
Network Bandwidth ◽  
High Space

Per-flow traffic measurement has emerged as a critical but challenging task in data centers in recent years in the face of massive network traffic. Many approximate methods have been proposed to resolve the existing resource-accuracy trade-off in per-flow traffic measurement, one of which is the sketch-based method. However, sketches are affected by their high computational cost and low throughput; moreover, their measurement accuracy is hard to guarantee under the conditions of changing network bandwidth or flow size distribution. Recently, FPGAplatforms have been widely deployed in data centers, as they demonstrate a good fit for high-speed network processing. In this work, we aim to address the problem of per-flow traffic measurement from a hardware architecture perspective. We thus design SAPTM, a pipelined systolic array-like architecture for high-throughput per-flow traffic measurement on FPGA. We adopt memory-friendly D-left hashing in the design of SAPTM, which guarantees high space utilization during flow insertion and eviction, successfully addressing the challenge of tracking a high-speed data stream under limited memory resources on FPGA. Evaluations on the Xilinx VCU118 platform with real-world benchmarks demonstrate that SAPTM possesses high space utilization. Comparisons with state-of-the-art sketch-based solutions show that SAPTM outperforms comparison methods in terms of throughput by a factor of 14.1x–70.5x without any accuracy loss.

High Throughput Realization of a New Systolic Array based FFT using CORDIC

2012 ◽  
Vol 2 (2) ◽  
pp. 53-59
Author(s):  
Gourav Jain ◽  
Shaik Rafi Ahamed
Keyword(s):  
Fourier Transform ◽  
Discrete Fourier Transform ◽  
High Throughput ◽  
Systolic Array ◽  
Digital Computer ◽  
High Speed ◽  
Clock Cycle ◽  
Complex Multiplication ◽  
Computer Complex ◽  
Dsp Applications

In this paper, the authors propose a new systolic array for radix-2, N-point discrete Fourier Transform (DFT) computation based on CORDIC (CO-ordinate Rotation Digital Computer). Complex multiplication can be done by this in a rather simple and elegant way. A CORDIC based multiplier less DFT architecture is designed in order to improve the performance of the system. It is able to provide two transforms per each clock cycle. The proposed design is well suited for high speed DSP-applications.

scholarly journals Fully Automated Cultivation of Adipose-Derived Stem Cells in the StemCellDiscovery—A Robotic Laboratory for Small-Scale, High-Throughput Cell Production Including Deep Learning-Based Confluence Estimation

Processes ◽  
2021 ◽  
Vol 9 (4) ◽  
pp. 575
Author(s):  
Jelena Ochs ◽  
Ferdinand Biermann ◽  
Tobias Piotrowski ◽  
Frederik Erkens ◽  
Bastian Nießing ◽  
...  
Keyword(s):  
Stem Cells ◽  
Deep Learning ◽  
High Throughput ◽  
High Speed ◽  
New Technologies ◽  
Human Mesenchymal Stem Cells ◽  
Simulation Software ◽  
System Capacity ◽  
Small Scale ◽  
Production Environment

Laboratory automation is a key driver in biotechnology and an enabler for powerful new technologies and applications. In particular, in the field of personalized therapies, automation in research and production is a prerequisite for achieving cost efficiency and broad availability of tailored treatments. For this reason, we present the StemCellDiscovery, a fully automated robotic laboratory for the cultivation of human mesenchymal stem cells (hMSCs) in small scale and in parallel. While the system can handle different kinds of adherent cells, here, we focus on the cultivation of adipose-derived hMSCs. The StemCellDiscovery provides an in-line visual quality control for automated confluence estimation, which is realized by combining high-speed microscopy with deep learning-based image processing. We demonstrate the feasibility of the algorithm to detect hMSCs in culture at different densities and calculate confluences based on the resulting image. Furthermore, we show that the StemCellDiscovery is capable of expanding adipose-derived hMSCs in a fully automated manner using the confluence estimation algorithm. In order to estimate the system capacity under high-throughput conditions, we modeled the production environment in a simulation software. The simulations of the production process indicate that the robotic laboratory is capable of handling more than 95 cell culture plates per day.

The Engagement of Hybrid Ultra High Space Division Multiplexing with Maximum Time Division Multiplexing Techniques for High-Speed Single-Mode Fiber Cable Systems

2019 ◽  
Vol 0 (0) ◽  
Author(s):  
I. S. Amiri ◽  
P. G. Kuppusamy ◽  
Ahmed Nabih Zaki Rashed ◽  
P. Jayarajan ◽  
M. R. Thiyagupriyadharsan ◽  
...  
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
Single Mode ◽  
Single Mode Fiber ◽  
Design Parameters ◽  
Control Parameters ◽  
Data Rates ◽  
Fiber Optic Communication ◽  
High Space ◽  
Optic Communication

AbstractHigh-speed single-mode fiber-optic communication systems have been presented based on various hybrid multiplexing schemes. Refractive index step and silica-doped germanium percentage parameters are also preserved during their technological boundaries of attention. It is noticed that the connect design parameters suffer more nonlinearity with the number of connects. Two different propagation techniques have been used to investigate the transmitted data rates as a criterion to enhance system performance. The first technique is soliton propagation, where the control parameters lead to equilibrium between the pulse spreading due to dispersion and the pulse shrinking because of nonlinearity. The second technique is the MTDM technique where the parameters are adjusted to lead to minimum dispersion. Two cases are investigated: no dispersion cancellation and dispersion cancellation. The investigations are conducted over an enormous range of the set of control parameters. Thermal effects are considered through three basic quantities, namely the transmission data rates, the dispersion characteristics, and the spectral losses.

High-speed and high-precision fluorescence-based cell count and viability assays using the Cellaca™ MX high-throughput cell counter

Cytotherapy ◽  
2021 ◽  
Vol 23 (5) ◽  
pp. S97
Author(s):  
J. Bell ◽  
Y. Huang ◽  
S. Yung ◽  
H. Qazi ◽  
C. Hernandez ◽  
...  
Keyword(s):  
Cell Count ◽  
High Precision ◽  
High Throughput ◽  
High Speed ◽  
Cell Counter

scholarly journals Event-Driven Simulation Scheme for Spiking Neural Networks Using Lookup Tables to Characterize Neuronal Dynamics

2006 ◽  
Vol 18 (12) ◽  
pp. 2959-2993 ◽  
Author(s):  
Eduardo Ros ◽  
Richard Carrillo ◽  
Eva M. Ortigosa ◽  
Boris Barbour ◽  
Rodrigo Agís
Keyword(s):  
Synaptic Plasticity ◽  
High Speed ◽  
Large Scale ◽  
Computational Cost ◽  
Brain Structures ◽  
Spike Timing ◽  
Neuronal Dynamics ◽  
Event Driven ◽  
Synaptic Dynamics

Nearly all neuronal information processing and interneuronal communication in the brain involves action potentials, or spikes, which drive the short-term synaptic dynamics of neurons, but also their long-term dynamics, via synaptic plasticity. In many brain structures, action potential activity is considered to be sparse. This sparseness of activity has been exploited to reduce the computational cost of large-scale network simulations, through the development of event-driven simulation schemes. However, existing event-driven simulations schemes use extremely simplified neuronal models. Here, we implement and evaluate critically an event-driven algorithm (ED-LUT) that uses precalculated look-up tables to characterize synaptic and neuronal dynamics. This approach enables the use of more complex (and realistic) neuronal models or data in representing the neurons, while retaining the advantage of high-speed simulation. We demonstrate the method's application for neurons containing exponential synaptic conductances, thereby implementing shunting inhibition, a phenomenon that is critical to cellular computation. We also introduce an improved two-stage event-queue algorithm, which allows the simulations to scale efficiently to highly connected networks with arbitrary propagation delays. Finally, the scheme readily accommodates implementation of synaptic plasticity mechanisms that depend on spike timing, enabling future simulations to explore issues of long-term learning and adaptation in large-scale networks.

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

scholarly journals Energy aware dynamic virtual machine consolidation in cloud data centers

2018 ◽  
Vol 7 (2.8) ◽  
pp. 550 ◽  
Author(s):  
G Anusha ◽  
P Supraja
Keyword(s):  
Energy Consumption ◽  
Virtual Machine ◽  
Data Centers ◽  
Energy Aware ◽  
Large Power ◽  
Complex Tasks ◽  
Cloud Data ◽  
Network Bandwidth ◽  
Virtual Machine Consolidation ◽  
Cloud Data Centers

Cloud computing is a growing technology now-a-days, which provides various resources to perform complex tasks. These complex tasks can be performed with the help of datacenters. Data centers helps the incoming tasks by providing various resources like CPU, storage, network, bandwidth and memory, which has resulted in the increase of the total number of datacenters in the world. These data centers consume large volume of energy for performing the operations and which leads to high operation costs. Resources are the key cause for the power consumption in data centers along with the air and cooling systems. Energy consumption in data centers is comparative to the resource usage. Excessive amount of energy consumption by datacenters falls out in large power bills. There is a necessity to increase the energy efficiency of such data centers. We have proposed an Energy aware dynamic virtual machine consolidation (EADVMC) model which focuses on pm selection, vm selection, vm placement phases, which results in the reduced energy consumption and the Quality of service (QoS) to a considerable level.

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