A Genetic-Driven Instruction Set for High Speed Network Processors

2006 ◽  
Author(s):  
H. Mohammadi ◽  
N. Yazdani
Keyword(s):  
High Speed ◽  
Instruction Set ◽  
Network Processors ◽  
High Speed Network

Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units

2007 ◽  
Vol 31 (3) ◽  
pp. 188-199 ◽  
Author(s):  
K. Vlachos ◽  
T. Orphanoudakis ◽  
Y. Papaeftathiou ◽  
N. Nikolaou ◽  
D. Pnevmatikatos ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
High Speed ◽  
Packet Processing ◽  
Network Processors ◽  
High Speed Network ◽  
And Performance ◽  
Processing Engine

PACKET INDEXING PROCESS OPTIMIZED FOR HIGH-SPEED NETWORK PROCESSORS

2005 ◽  
Vol 14 (04) ◽  
pp. 841-860 ◽  
Author(s):  
C. CHAROPOULOS ◽  
F. ANDRITSOPOULOS ◽  
Y. MITSOS ◽  
G. DOUMENIS ◽  
G. STASINOPOULOS
Keyword(s):  
High Speed ◽  
High Performance ◽  
Packet Classification ◽  
Network Processors ◽  
High Speed Network ◽  
Packet Data ◽  
Content Addressable Memories ◽  
Open Addressing ◽  
Discrete Flow ◽  
Significant Size

Most network processors perform some kind of classification on the received packet stream, according to criteria set by the implemented networking application. Packet indexing is an integral part of the packet classification process. Indexing is considered as one of the most processor intensive part of network processing and is often supported by special hardware units. High performance Network processors usually rely upon Content Addressable Memories (CAMs) for the indexing of millions of packets per second into discrete "flow Identifiers" in ATM and IP networks. Most often, the indexing process examines packet data (tags) of significant size, necessitating the use of large CAM devices. This paper proposes an alternative method for searching lengthy tags, using RAM as storage medium instead of the expensive and complex CAMs. The technique applies the open-addressing hashing methodology to provide high speed lookups, close to CAM's performance. Our approach handles efficiently the limitations imposed by the hashing algorithms by appropriately selecting system parameters and resolving hashing collisions. The advantages of the proposed method are evaluated in detail.

Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Computation Time ◽  
Digital Signal ◽  
Instruction Set ◽  
Computationally Efficient ◽  
Specific Instruction ◽  
Processor Core ◽  
Speed Performance ◽  
Application Specific

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

scholarly journals WebRTC - Realtime Communication for the Open Web Platform

Queue ◽  
2021 ◽  
Vol 19 (1) ◽  
pp. 77-93
Author(s):  
Niklas Blum ◽  
Serge Lachapelle ◽  
Harald Alvestrand
Keyword(s):  
High Speed ◽  
Network Access ◽  
The Past ◽  
Human Contact ◽  
High Speed Network ◽  
The World ◽  
Web Platform

In this time of pandemic, the world has turned to Internet-based, RTC (realtime communication) as never before. The number of RTC products has, over the past decade, exploded in large part because of cheaper high-speed network access and more powerful devices, but also because of an open, royalty-free platform called WebRTC. WebRTC is growing from enabling useful experiences to being essential in allowing billions to continue their work and education, and keep vital human contact during a pandemic. The opportunities and impact that lie ahead for WebRTC are intriguing indeed.

Sign in / Sign up

Export Citation Format

Share Document