Analog performance of submicron GC SOI MOSFETs

2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) ◽

10.1109/iccdcs.2012.6188930 ◽

2012 ◽

Cited By ~ 2

Author(s):

J. P. Nemer ◽

M. de Souza ◽

M. A. Pavanello ◽

D. Flandre

Keyword(s):

Analog Performance

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Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors

2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) ◽

10.1109/iccdcs.2014.7016159 ◽

2014 ◽

Cited By ~ 2

Author(s):

R. Assalti ◽

M. A. Pavanello ◽

M. de Souza ◽

D. Flandre

Keyword(s):

Technological Parameters ◽

Analog Performance

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Effects of channel barrier layer on the analog performance of p-Ge/ n-InGaAs CMOS devices

2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking ◽

10.1109/et2ecn.2014.7044938 ◽

2014 ◽

Author(s):

Suchismita Tewari ◽

Abhijit Biswas ◽

Abhijit Mallik

Keyword(s):

Barrier Layer ◽

Analog Performance

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An analog performance estimator for improving the effectiveness of CMOS analog systems circuit synthesis

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) ◽

10.1109/date.1999.761156 ◽

2003 ◽

Cited By ~ 2

Author(s):

A. Nunez-Aldana ◽

R. Vemuri

Keyword(s):

Circuit Synthesis ◽

Analog Performance ◽

Analog Systems

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RF/Analog performance of GaAs Multi-Fin FinFET with stress effect

Microelectronics Journal ◽

10.1016/j.mejo.2021.105267 ◽

2021 ◽

Vol 117 ◽

pp. 105267

Author(s):

Rinku Rani Das ◽

Santanu Maity ◽

Atanu Chowdhury ◽

Apurba Chakraborty

Keyword(s):

Stress Effect ◽

Analog Performance

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Prediction of analog performance parameters using oscillation based test

22nd IEEE VLSI Test Symposium, 2004. Proceedings. ◽

10.1109/vtest.2004.1299267 ◽

2004 ◽

Cited By ~ 23

Author(s):

A. Raghunathan ◽

Hong Joong Shin ◽

J.A. Abraham ◽

A. Chatterjee

Keyword(s):

Performance Parameters ◽

Analog Performance

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Charge-plasma based dual-material and gate-stacked architecture of junctionless transistor for enhanced analog performance

Superlattices and Microstructures ◽

10.1016/j.spmi.2015.10.017 ◽

2015 ◽

Vol 88 ◽

pp. 582-590 ◽

Cited By ~ 19

Author(s):

S. Intekhab Amin ◽

R.K. Sarin

Keyword(s):

Charge Plasma ◽

Analog Performance ◽

Junctionless Transistor ◽

Dual Material

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Analog Performance of Multiple-quantum-well Electroabsorption Modulator

Optical and Quantum Electronics ◽

10.1007/s11082-005-0957-2 ◽

2005 ◽

Vol 37 (11) ◽

pp. 1025-1031 ◽

Cited By ~ 2

Author(s):

Y. S. Yun ◽

Y. W. Choi ◽

J. D. Chung ◽

J. H. Kim

Keyword(s):

Quantum Well ◽

Multiple Quantum Well ◽

Multiple Quantum ◽

Electroabsorption Modulator ◽

Analog Performance

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Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309218 ◽

2017 ◽

Author(s):

R. Assalti ◽

M. de Souza ◽

M. Casse ◽

S. Barraud ◽

G. Reimbold ◽

...

Keyword(s):

Low Power ◽

Analog Performance ◽

Self Cascode

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Air-spacers as analog-performance booster for 5 nm-node N-channel nanosheet transistor

Semiconductor Science and Technology ◽

10.1088/1361-6641/ac16e6 ◽

2021 ◽

Author(s):

Yogendra Pratap Pundir ◽

Arvind Bisht ◽

Rajesh Saha ◽

Pankaj Kumar Pal

Keyword(s):

Analog Performance

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Investigation of Analog Performance of In0.53Ga0.47As-Based Nanotube Double-Gate-All-Around (DGAA) MOSFET

Lecture Notes in Electrical Engineering - Recent Trends in Electronics and Communication ◽

10.1007/978-981-16-2761-3_8 ◽

2021 ◽

pp. 89-96

Author(s):

Nitish Kumar ◽

Himanshi Awasthi ◽

Vaibhav Purwar ◽

Abhinav Gupta ◽

Sanjeev Rai

Keyword(s):

Double Gate ◽

Analog Performance

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