3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time

2014 ◽  
Author(s):  
Ishan G Thakkar ◽  
Sudeep Pasricha
Keyword(s):  
Random Access ◽  
Access Time ◽  
High Bandwidth

scholarly journals In-DRAM Cache Management for Low Latency and Low Power 3D-Stacked DRAMs

Micromachines ◽  
2019 ◽  
Vol 10 (2) ◽  
pp. 124 ◽  
Author(s):  
Ho Shin ◽  
Eui-Young Chung
Keyword(s):  
Low Power ◽  
High Performance ◽  
High Capacity ◽  
Random Access ◽  
Computing System ◽  
Access Time ◽  
Low Latency ◽  
Cache Management ◽  
Long Latency ◽  
High Bandwidth

Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed, which are more attractive for high-capacity DRAMs because they can be implemented at a lower cost in 3D-stacked DRAMs. However, most research mainly focuses on the architecture of the in-DRAM cache itself and does not pay much attention to proper management methods. In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, we demonstrate the improvement of energy delay product up to 67%.

scholarly journals Pre-Emphasis Pulse Design for Random-Access Memory

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1454
Author(s):  
Yoshihiro Sugiura ◽  
Toru Tanzawa
Keyword(s):  
Time Constant ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Memory Access ◽  
Access Time ◽  
Access Memory ◽  
Delay Times ◽  
Cell Current ◽  
The Impact

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.

Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices

2020 ◽  
pp. 2150106
Author(s):  
Harekrishna Kumar ◽  
V. K. Tomar
Keyword(s):  
Power Dissipation ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Time ◽  
Access Memory ◽  
Subthreshold Region ◽  
Noise Margin ◽  
Static Noise

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the [Formula: see text] ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiation-hardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages.

A Precise Implementation of Random Access Time Measurement for Embedded SRAM

2019 ◽  
Vol 100 (5) ◽  
pp. 525-528
Author(s):  
L. J. Zhang ◽  
Z. O. Wang ◽  
Y. F. Zhang ◽  
Y. Z. Li ◽  
L. F. Mao
Keyword(s):  
Random Access ◽  
Time Measurement ◽  
Access Time ◽  
Embedded Sram

Broadcast Data Placement over Multiple Wireless Channels

2011 ◽  
pp. 155-176
Author(s):  
Dimitrios Katsaros ◽  
Yannis Manolopoulos
Keyword(s):  
Wireless Channels ◽  
Effective Means ◽  
Communication Technologies ◽  
Wireless Channel ◽  
Optimal Placement ◽  
Access Time ◽  
Portable Devices ◽  
High Bandwidth ◽  
Mobile Clients

The advances in computer and communication technologies made possible an ubiquitous computing environment were clients equipped with portable devices can send and receive data anytime and from anyplace. Due to the asymmetry in communication and the scarceness of wireless resources, data broadcast is widely employed as an effective means in delivering data to the mobile clients. For reasons like heterogeneous communication capabilities and variable quality of service offerings, we may need to divide a single wireless channel into multiple physical or logical channels. Thus, we need efficient algorithms for placing the broadcast data into these multiple channels so as to reduce the client access time. The present chapter discusses algorithms for placing broadcast data to multiple wireless channels, which cannot be coalesced into a lesser number of high-bandwidth channels, assuming that there are no dependencies among the transmitted data. We give an algorithm for obtaining the optimal placement to the channels and explain its limitation since it is computationally very demanding and thus unfeasible. Then, we present heuristic schemes for obtaining suboptimal solutions to the problem of reporting on their implementation cost and their relative performance.

Atomic Force High Frequency Phonons Non-volatile Dynamic Random-Access Memory Compatible with Sub-7nm ULSI CMOS Technology

MRS Advances ◽  
2019 ◽  
Vol 4 (48) ◽  
pp. 2577-2584
Author(s):  
James N. Pan
Keyword(s):  
Quantum Wells ◽  
High Frequency ◽  
Nonvolatile Memory ◽  
High Speed ◽  
Random Access ◽  
Cost Effective ◽  
Cmos Technology ◽  
Access Time ◽  
Cmos Process ◽  
Atomic Force

ABSTRACTThis paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and random accessed magnetic devices. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of only one transistor (MOSFET) – small size, and more cost effective, compared with a 6-Transistor SRAM. There is no need to refresh, as required by DRAM. The access time can be less than 1ns – close to the speed level of relaxation time - much faster than traditional FLASH memories and comparable to volatile DRAM. The operating voltages for all memory functions can be as low as high speed CMOS.

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