A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faults

2011 ◽  
Author(s):  
Reyhaneh Jabbarvand Behrouz ◽  
Mehdi Modarressi ◽  
Hamid Sarbazi Azad
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Permanent Faults ◽  
On Chip

Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems

2017 ◽  
Vol 28 (3) ◽  
pp. 838-849 ◽  
Author(s):  
Yu-Yin Chen ◽  
En-Jui Chang ◽  
Hsien-Kai Hsin ◽  
Kun-Chih Chen ◽  
An-Yeu Andy Wu
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Path Diversity ◽  
On Chip

A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip

2017 ◽  
Vol 27 (02) ◽  
pp. 1850022 ◽  
Author(s):  
Ling Wang ◽  
Terrence Mak
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Mesh Network ◽  
Communication Performance ◽  
Simulation Results ◽  
On Chip

In 2D mesh Network on Chips (NoCs), fault-tolerant algorithms usually deactivate healthy nodes to form rectangular or convex fault blocks. However, the deactivated nodes can possibly form an available tunnel in a faulty block. We propose a method to discover these tunnels, and propose a fault-tolerant routing algorithm to route messages through such paths such that the overall communication performance is improved. In addition, the algorithm is deadlock-free by prohibiting some turns. Simulation results demonstrate that the reuse of the sacrificed nodes in fault blocks can significantly reduce the average message latency.

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