A microeconomic model for simultaneous gate sizing and voltage scaling for power optimization

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240907 ◽

2004 ◽

Cited By ~ 1

Author(s):

N. Ranganathan ◽

A.K. Murugavel

Keyword(s):

Power Optimization ◽

Voltage Scaling ◽

Gate Sizing

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Power reduction through iterative gate sizing and voltage scaling

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349) ◽

10.1109/iscas.1999.777849 ◽

2003 ◽

Author(s):

Chingwei Yeh ◽

Min-Cheng Chang ◽

Shih-Chieh Chang ◽

Wen-Bone Jone

Keyword(s):

Voltage Scaling ◽

Power Reduction ◽

Gate Sizing

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General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2008.2003268 ◽

2008 ◽

Vol 27 (10) ◽

pp. 1788-1797 ◽

Cited By ~ 17

Author(s):

F. Dabiri ◽

A. Nahapetian ◽

T. Massey ◽

M. Potkonjak ◽

M. Sarrafzadeh

Keyword(s):

Power Optimization ◽

Soft Error ◽

Gate Sizing ◽

General Methodology

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Soft Error-Aware Power Optimization Using Gate Sizing

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/978-3-540-74442-9_25 ◽

2007 ◽

pp. 255-267 ◽

Cited By ~ 2

Author(s):

Foad Dabiri ◽

Ani Nahapetian ◽

Miodrag Potkonjak ◽

Majid Sarrafzadeh

Keyword(s):

Power Optimization ◽

Soft Error ◽

Gate Sizing

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A power optimization method considering glitch reduction by gate sizing

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379) ◽

10.1145/280756.280907 ◽

1998 ◽

Cited By ~ 11

Author(s):

Masanori Hashimoto ◽

Hidetoshi Onodera ◽

Keikichi Tamaru

Keyword(s):

Power Optimization ◽

Optimization Method ◽

Gate Sizing ◽

Glitch Reduction

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Glitch elimination by gate freezing, gate sizing and buffer insertion for low power optimization circuit

30th Annual Conference of IEEE Industrial Electronics Society, 2004. IECON 2004 ◽

10.1109/iecon.2004.1432125 ◽

2005 ◽

Cited By ~ 3

Author(s):

Hyungwoo Lee ◽

Hakgun Shin ◽

Juho Kim

Keyword(s):

Low Power ◽

Power Optimization ◽

Gate Sizing ◽

Buffer Insertion

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Power reduction by simultaneous voltage scaling and gate sizing

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106) ◽

10.1109/aspdac.2000.835120 ◽

2002 ◽

Author(s):

Chunhong Chen ◽

M. Sarrafzadeh

Keyword(s):

Voltage Scaling ◽

Power Reduction ◽

Gate Sizing

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Power optimization in multipliers using multi-precision combined with voltage scaling techniques

10.1109/asqed.2009.5206295 ◽

2009 ◽

Author(s):

Xiaoxiao Zhang ◽

Amine Bermak ◽

Farid Boussaid

Keyword(s):

Power Optimization ◽

Voltage Scaling

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Simultaneous voltage scaling and gate sizing for low-power design

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ◽

10.1109/tcsii.2002.802964 ◽

2002 ◽

Vol 49 (6) ◽

pp. 400-408 ◽

Cited By ~ 20

Author(s):

Chunhong Chen ◽

M. Sarrafzadeh

Keyword(s):

Low Power ◽

Low Power Design ◽

Voltage Scaling ◽

Gate Sizing

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Dynamic voltage scaling with links for power optimization of interconnection networks

The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. ◽

10.1109/hpca.2003.1183527 ◽

2003 ◽

Cited By ~ 192

Author(s):

Li Shang ◽

Li-Shiuan Peh ◽

N.K. Jha

Keyword(s):

Interconnection Networks ◽

Power Optimization ◽

Voltage Scaling ◽

Dynamic Voltage Scaling ◽

Dynamic Voltage

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A power optimization method considering glitch reduction by gate sizing

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379) ◽

10.1109/lpe.1998.708192 ◽

2002 ◽

Cited By ~ 2

Author(s):

M. Hashimoto ◽

H. Onodera ◽

K. Tamaru

Keyword(s):

Power Optimization ◽

Optimization Method ◽

Gate Sizing ◽

Glitch Reduction

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