A power optimization method considering glitch reduction by gate sizing
Keyword(s):
2012 ◽
Vol 35
(5)
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pp. 979-989
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Keyword(s):
2008 ◽
Vol 27
(10)
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pp. 1788-1797
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2014 ◽
Vol 1008-1009
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pp. 421-425
2014 ◽
Vol 971-973
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pp. 979-982