Design of resonant global clock distributions

2004 ◽  
Author(s):  
S.C. Chan ◽  
K.L. Shepard ◽  
P.J. Restle
Keyword(s):  
Global Clock ◽  
Clock Distributions

Comparison between electrical and optical global clock distributions for CMOS integrated circuits

2005 ◽  
Vol 44 (10) ◽  
pp. 105402 ◽  
Author(s):  
Eric Cassan ◽  
Delphine Marris ◽  
Mathieu Rouvière ◽  
Laurent Vivien ◽  
Suzanne Laval
Keyword(s):  
Integrated Circuits ◽  
Cmos Integrated Circuits ◽  
Global Clock ◽  
Clock Distributions

Uniform-phase uniform-amplitude resonant-load global clock distributions

2005 ◽  
Vol 40 (1) ◽  
pp. 102-109 ◽  
Author(s):  
S.C. Chan ◽  
K.L. Shepard ◽  
P.J. Restle
Keyword(s):  
Global Clock ◽  
Clock Distributions

Molecular phylogeny and divergence time estimates of Penaeid Shrimp Lineages (Decapoda: Penaeidae)

Zootaxa ◽  
2009 ◽  
Vol 2107 (1) ◽  
pp. 41-52 ◽  
Author(s):  
CAROLINA M VOLOCH ◽  
PABLO R FREIRE ◽  
CLAUDIA A M RUSSO
Keyword(s):  
Fossil Record ◽  
Divergence Time ◽  
Penaeid Shrimp ◽  
Divergence Time Estimates ◽  
Time Estimates ◽  
Global Clock ◽  
Late Tertiary ◽  
The Family ◽  
Molecular Studies ◽  
Triassic Period

Fossil record of penaeids indicates that the family exists since the Triassic period, but extant genera appeared only recently in Tertiary strata. Molecular based divergence time estimates on the matter of penaeid radiation were never properly addressed, due to shortcomings of the global molecular clock assumptions. Here, we studied the diversification patterns of the family, uncovering, more specifically, a correlation between fossil and extant Penaeid fauna. For this, we have used a Bayesian framework that does not assume a global clock. Our results suggest that Penaeid genera originated between 20 million years ago and 43 million years ago, much earlier than expected by previous molecular studies. Altogether, these results promptly discard late Tertiary or even Quaternary hypotheses that presumed a major glaciations influence on the diversification patterns of the family.

scholarly journals Design of Completion Detectors in Asynchronous Communication System

2020 ◽  
Vol 9 (3) ◽  
pp. 3329-3334
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Communication System ◽  
Implementation Process ◽  
Asynchronous Communication ◽  
Digital Design ◽  
Low Power Consumption ◽  
Asynchronous Design ◽  
Global Clock ◽  
On Chip

In digital design, there are two types of design, synchronous design and asynchronous design. In synchronous design, global clock is one of the main system that consume a lot of power. The power in synchronous design is consumed by clock even if there is no data processing take place. The asynchronous design that depends on data is clockless and as far as the power is concerned, asynchronous design does not consume much power compared with synchronous design and this really make asynchronus design the preffered choice for low power consumption. Besides having low power consumption, there are many advantages of aynchronous design compared with synchronous design. This paper proposed new dual rail completion detector (CD), 3-6 CD, 2-7 CD and 1-4 CD for on-chip communication that are used widely in an asynchronous communication system. The design of CD is based on the principle of sum adder. The circuit is designed by using Altera Quartus II CAD tools, synthesis and implementation process is executed to check the syntax error of the design. The design proved to be successful by using asynchronous on-chip communication in the simulation.

scholarly journals Organising LTL monitors over distributed systems with a global clock

2016 ◽  
Vol 49 (1-2) ◽  
pp. 109-158 ◽  
Author(s):  
Christian Colombo ◽  
Yliès Falcone
Keyword(s):  
Distributed Systems ◽  
Global Clock

scholarly journals Energy Efficiency Due to a Common Global Timebase—Synchronizing FlexRay to 802.1AS Networks as a Foundation

2018 ◽  
Vol 8 (3) ◽  
pp. 26
Author(s):  
Paul Milbredt ◽  
Efim Schick ◽  
Michael Hübner
Keyword(s):  
Time Synchronization ◽  
Fault Tolerant ◽  
Low Cost ◽  
Autonomous Driving ◽  
Consumer Electronics ◽  
Area Network ◽  
Control Applications ◽  
Synchronization Mechanism ◽  
Global Clock ◽  
Time And Energy

Modern automotive control applications require a holistic time-sensitive development. Nowadays, this is achieved by technologies specifically designed for the automotive domain, like FlexRay, which offer a fault-tolerant time synchronization mechanism built into the protocol. Currently, the automotive industry adopts the Ethernet within the car, not only for embedding consumer electronics, but also as a fast and reliable backbone for control applications. Still, low-cost but highly reliable sensors connected over the traditional Controller Area Network (CAN) deliver data needed for autonomous driving. To fusion the data efficiently among all, a common timebase is required. The alternative would be oversampling, which uses more time and energy, e.g., at least double the perception rates of sensors. Ethernet and CAN do require the latter by default. Hence, a global synchronization mechanism eases tremendously the design of a low power automotive network and is the foundation of a transparent global clock. In this article, we present the first step: Synchronizing legacy FlexRay networks to the upcoming Ethernet backbone, which will contain a precise clock over the generalized Precision Time Protocol (gPTP) defined in IEEE 802.1AS. FlexRay then could still drive its strengths with deterministic transmission behavior and possibly also serve as a redundant technology for fail-operational system design.

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