Low Power Resonant Rotary Global Clock Distribution Network Design

Mapping Intimacies ◽

10.17918/etd-4573 ◽

2021 ◽

Author(s):

Ying Teng

Keyword(s):

Low Power ◽

Network Design ◽

Distribution Network ◽

Clock Distribution ◽

Distribution Network Design ◽

Global Clock ◽

Clock Distribution Network

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Power Efficient 3D Clock Distribution Network Design with TSV Count Optimization

Procedia Computer Science ◽

10.1016/j.procs.2016.07.197 ◽

2016 ◽

Vol 93 ◽

pp. 169-175 ◽

Cited By ~ 2

Author(s):

Nikhil Joshi ◽

John Reuben

Keyword(s):

Network Design ◽

Distribution Network ◽

Clock Distribution ◽

Power Efficient ◽

Distribution Network Design ◽

Clock Distribution Network

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Clock distribution network design for single phase energy recovery circuits

2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2) ◽

10.1109/icnets2.2017.8067969 ◽

2017 ◽

Author(s):

Nunna Yamini ◽

P. Sasipriya ◽

V.S. Kanchana Bhaaskaran

Keyword(s):

Network Design ◽

Energy Recovery ◽

Single Phase ◽

Distribution Network ◽

Clock Distribution ◽

Distribution Network Design ◽

Clock Distribution Network

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Timing analysis for thermally robust clock distribution network design for 3D ICs

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems ◽

10.1109/epeps.2013.6703469 ◽

2013 ◽

Cited By ~ 3

Author(s):

Sung Joo Park ◽

Nitish Natu ◽

Madhavan Swaminathan ◽

Byunghyun Lee ◽

Sang Min Lee ◽

...

Keyword(s):

Network Design ◽

Timing Analysis ◽

Distribution Network ◽

Clock Distribution ◽

Distribution Network Design ◽

3D Ics ◽

Clock Distribution Network

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A Self-Adaptive and PVT Insensitive Clock Distribution Network Design for High-Speed Memory Interfaces

2009 IEEE Workshop on Microelectronics and Electron Devices ◽

10.1109/wmed.2009.4816147 ◽

2009 ◽

Cited By ~ 2

Author(s):

Feng Lin ◽

Brent Keeth

Keyword(s):

Network Design ◽

High Speed ◽

Distribution Network ◽

Clock Distribution ◽

Distribution Network Design ◽

Clock Distribution Network ◽

Self Adaptive

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Cost-effective SET-tolerant clock distribution network design by mitigating single event transient propagation

Science China Information Sciences ◽

10.1007/s11432-016-9041-5 ◽

2017 ◽

Vol 60 (10) ◽

Author(s):

Peipei Hao ◽

Shuming Chen ◽

Pengcheng Huang ◽

Jianjun Chen ◽

Bin Liang

Keyword(s):

Network Design ◽

Distribution Network ◽

Cost Effective ◽

Clock Distribution ◽

Single Event ◽

Single Event Transient ◽

Distribution Network Design ◽

Clock Distribution Network

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Automation of clock distribution network design for digital integrated circuits using divide and conquer technique

Integration ◽

10.1016/j.vlsi.2005.08.001 ◽

2006 ◽

Vol 39 (4) ◽

pp. 407-419 ◽

Cited By ~ 1

Author(s):

Anu Gupta ◽

Bipin Kulkarni

Keyword(s):

Integrated Circuits ◽

Network Design ◽

Distribution Network ◽

Divide And Conquer ◽

Clock Distribution ◽

Digital Integrated Circuits ◽

Distribution Network Design ◽

Clock Distribution Network

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Frequency-centric resonant rotary clock distribution network design

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) ◽

10.1109/iccad.2014.7001434 ◽

2014 ◽

Cited By ~ 2

Author(s):

Ying Teng ◽

Baris Taskin

Keyword(s):

Network Design ◽

Distribution Network ◽

Clock Distribution ◽

Distribution Network Design ◽

Clock Distribution Network

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A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology

2011 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2011.80 ◽

2011 ◽

Cited By ~ 4

Author(s):

Naveen Kumar Kancharapu ◽

Marshnil Dave ◽

Veerraju Masimukkula ◽

Maryam Shojaei Baghini ◽

Dinesh Kumar Sharma

Keyword(s):

Low Power ◽

Distribution Network ◽

Current Mode ◽

Cmos Technology ◽

Clock Distribution ◽

Clock Distribution Network

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Design of Low power & High Performance Multi Source H-Tree Clock Distribution Network

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) ◽

10.1109/vlsidcs47293.2020.9179954 ◽

2020 ◽

Author(s):

V.G. Srivatsa ◽

Arunkumar P. Chavan ◽

Divakar Mourya

Keyword(s):

Low Power ◽

High Performance ◽

Distribution Network ◽

Clock Distribution ◽

Clock Distribution Network

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An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2020.3003091 ◽

2020 ◽

Vol 28 (9) ◽

pp. 2042-2054

Author(s):

Qian Ding ◽

Graham Knight ◽

Terrence Mak

Keyword(s):

Low Power ◽

Distribution Network ◽

Clock Distribution ◽

Clock Distribution Network ◽

Many Core

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