scholarly journals Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding

2003 ◽  
Author(s):  
P.M. Rosinger ◽  
B.M. Al-Hashimi ◽  
N. Nicolici
Keyword(s):  
Low Power ◽  
Mixed Mode ◽  
Pattern Generation ◽  
Mask Pattern

An Ultra-low-power Mixed-mode Face Recognition Processor for Always-on User Authentication in Mobile Device

2020 ◽  
Vol 20 (6) ◽  
pp. 499-509
Author(s):  
Ji-Hoon Kim ◽  
Changhyeon Kim ◽  
Kwantae Kim ◽  
Juhyoung Lee ◽  
Hoi-Jun Yoo ◽  
...  
Keyword(s):  
Face Recognition ◽  
Low Power ◽  
Mobile Device ◽  
Mixed Mode ◽  
User Authentication ◽  
Ultra Low Power

scholarly journals Low Power Restricted Boltzmann Machine Using Mixed-Mode Magneto-Tunneling Junctions

2019 ◽  
Vol 40 (2) ◽  
pp. 345-348 ◽  
Author(s):  
Shamma Nasrin ◽  
Justine L. Drobitch ◽  
Supriyo Bandyopadhyay ◽  
Amit Ranjan Trivedi
Keyword(s):  
Low Power ◽  
Mixed Mode ◽  
Restricted Boltzmann Machine ◽  
Boltzmann Machine ◽  
Tunneling Junctions

A Case Study: Low Power Design-for-Testability Features of a Multi-Core Processor Godson-T

2011 ◽  
Vol 301-303 ◽  
pp. 1237-1242
Author(s):  
Da Wang ◽  
Dong Rui Fan ◽  
Yu Hu
Keyword(s):  
Low Power ◽  
Modular Design ◽  
Multicore Processors ◽  
Low Power Design ◽  
Design For Testability ◽  
Deep Submicron ◽  
Pattern Generation ◽  
Test Time ◽  
Test Power ◽  
Multi Core Processor

This paper describes the low power test challenges and features of a multi-core processor, Godson-T, which contains 16 identical cores. Since the silicon design technology scales to ultra deep submicron and even nanometers, the complexity and cost of testing is growing up, and the test power of such designs is extremely curious, especially for multicore processors. In this paper, we use the modular design methodology and scaleable design-for-testability (DFT) structure to achieve low test power, at the same time, an improved test pattern generation method is studied to reduce test power further more. The experimental results from the real chip show that the test power and test time are well balanced while achieving acceptable test coverage and cost.

A low power test pattern generation for built-in self-test based circuits

2011 ◽  
Vol 98 (3) ◽  
pp. 301-309 ◽  
Author(s):  
Bo Ye ◽  
Tianwang Li ◽  
Qian Zhao ◽  
Duo Zhou ◽  
Xiaohua Wang ◽  
...  
Keyword(s):  
Low Power ◽  
Test Pattern ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Power Test ◽  
Low Power Test ◽  
Self Test ◽  
Built In Self Test

Characterization of an integrated multibeam laser mask-pattern generation and dry etch processing total solution

2002 ◽  
Author(s):  
Alex H. Buxbaum ◽  
Melisa J. Buie ◽  
Brigitte C. Stoehr ◽  
Warren Montgomery ◽  
Scott E. Fuller
Keyword(s):  
Pattern Generation ◽  
Mask Pattern ◽  
Dry Etch
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