Speculative trace scheduling in VLIW processors

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.2002.1106803 ◽

2003 ◽

Cited By ~ 5

Author(s):

M. Agarwal ◽

S.K. Nandy

Keyword(s):

Vliw Processors ◽

Trace Scheduling

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Multithreaded architectural support for speculative trace scheduling in VLIW processors

Proceedings. 15th Symposium on Integrated Circuits and Systems Design ◽

10.1109/sbcci.2002.1137635 ◽

2003 ◽

Cited By ~ 1

Author(s):

M. Agarwal ◽

S.K. Nandy ◽

J. v Eijndhoven ◽

S. Balakrishanan

Keyword(s):

Vliw Processors ◽

Architectural Support ◽

Trace Scheduling

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Branch prediction techniques for low-power VLIW processors

Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03 ◽

10.1145/764808.764866 ◽

2003 ◽

Cited By ~ 7

Author(s):

G. Palermo ◽

M. Sam ◽

C. Silvan ◽

V. Zaccari ◽

R. Zafalo

Keyword(s):

Low Power ◽

Branch Prediction ◽

Vliw Processors ◽

Prediction Techniques

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Single-chip multi-processor integrating quadruple 8-way vliw processors with interface timing analysis considering power supply noise

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594741 ◽

2006 ◽

Author(s):

S. Imai ◽

A. Inoue ◽

M. Matsumura ◽

K. Kawasaki ◽

A. Suga

Keyword(s):

Power Supply ◽

Timing Analysis ◽

Power Supply Noise ◽

Single Chip ◽

Vliw Processors ◽

Supply Noise

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An efficient heuristic for instruction scheduling on clustered vliw processors

Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems - CASES '11 ◽

10.1145/2038698.2038707 ◽

2011 ◽

Cited By ~ 5

Author(s):

Xuemeng Zhang ◽

Hui Wu ◽

Jingling Xue

Keyword(s):

Instruction Scheduling ◽

Vliw Processors

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Making wide-issue VLIW processors viable on FPGAs

ACM Transactions on Architecture and Code Optimization ◽

10.1145/2086696.2086712 ◽

2012 ◽

Vol 8 (4) ◽

pp. 1-16 ◽

Cited By ~ 8

Author(s):

Madhura Purnaprajna ◽

Paolo Ienne

Keyword(s):

Vliw Processors ◽

Wide Issue

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Reducing the complexity of instruction-level power models for VLIW processors

Design Automation for Embedded Systems ◽

10.1007/s10617-006-9045-5 ◽

2005 ◽

Vol 10 (1) ◽

pp. 49-67 ◽

Cited By ~ 6

Author(s):

A. Bona ◽

M. Sami ◽

D. Sciuto ◽

C. Silvano ◽

V. Zaccaria ◽

...

Keyword(s):

Vliw Processors ◽

Power Models

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Variable-based multi-module data caches for clustered VLIW processors

14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05) ◽

10.1109/pact.2005.40 ◽

2005 ◽

Cited By ~ 3

Author(s):

E. Gibert ◽

J. Abella ◽

J. Sanchez ◽

X. Vera ◽

A. Gonzalez

Keyword(s):

Vliw Processors ◽

Data Caches

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Integrating VLIW Processors with a Network on Chip

Lecture Notes in Computer Science - Embedded Computer Systems: Architectures, Modeling, and Simulation ◽

10.1007/978-3-540-73625-7_2 ◽

2007 ◽

pp. 2-2

Author(s):

Jos Huisken

Keyword(s):

Network On Chip ◽

Vliw Processors ◽

On Chip

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WCET-aware hyper-block construction for clustered VLIW processors

Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems - LCTES 2019 ◽

10.1145/3316482.3326349 ◽

2019 ◽

Cited By ~ 1

Author(s):

Xuesong Su ◽

Hui Wu ◽

Jingling Xue

Keyword(s):

Vliw Processors ◽

Block Construction

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Issue-Slot Based Predication Encoding Technique for VLIW Processors

2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST) ◽

10.1109/mocast49295.2020.9200304 ◽

2020 ◽

Author(s):

Lukas Gerlach ◽

Fabian Stuckmann ◽

Holger Blume ◽

Guillermo Paya-Vaya

Keyword(s):

Vliw Processors

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