Variable-based multi-module data caches for clustered VLIW processors

14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05) ◽

10.1109/pact.2005.40 ◽

2005 ◽

Cited By ~ 3

Author(s):

E. Gibert ◽

J. Abella ◽

J. Sanchez ◽

X. Vera ◽

A. Gonzalez

Keyword(s):

Vliw Processors ◽

Data Caches

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Branch prediction techniques for low-power VLIW processors

Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03 ◽

10.1145/764808.764866 ◽

2003 ◽

Cited By ~ 7

Author(s):

G. Palermo ◽

M. Sam ◽

C. Silvan ◽

V. Zaccari ◽

R. Zafalo

Keyword(s):

Low Power ◽

Branch Prediction ◽

Vliw Processors ◽

Prediction Techniques

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Low Energy Associative Data Caches for Embedded Systems

Embedded Software for SoC ◽

10.1007/0-306-48709-8_37 ◽

2005 ◽

pp. 513-525

Author(s):

Dan Nicolaescu ◽

Alex Veidenbaum ◽

Alex Nicolau

Keyword(s):

Embedded Systems ◽

Low Energy ◽

Data Caches

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Single-chip multi-processor integrating quadruple 8-way vliw processors with interface timing analysis considering power supply noise

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594741 ◽

2006 ◽

Author(s):

S. Imai ◽

A. Inoue ◽

M. Matsumura ◽

K. Kawasaki ◽

A. Suga

Keyword(s):

Power Supply ◽

Timing Analysis ◽

Power Supply Noise ◽

Single Chip ◽

Vliw Processors ◽

Supply Noise

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An efficient heuristic for instruction scheduling on clustered vliw processors

Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems - CASES '11 ◽

10.1145/2038698.2038707 ◽

2011 ◽

Cited By ~ 5

Author(s):

Xuemeng Zhang ◽

Hui Wu ◽

Jingling Xue

Keyword(s):

Instruction Scheduling ◽

Vliw Processors

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NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution

International Journal of Reconfigurable Computing ◽

10.1155/2012/915178 ◽

2012 ◽

Vol 2012 ◽

pp. 1-12 ◽

Cited By ~ 2

Author(s):

Kaveh Aasaraai ◽

Andreas Moshovos

Keyword(s):

High Efficiency ◽

Main Memory ◽

Data Cache ◽

Improve Performance ◽

Data Caches ◽

Content Addressable Memories ◽

Processor Designs ◽

Level Parallelism ◽

Order Execution ◽

Runahead Execution

Soft processors often use data caches to reduce the gap between processor and main memory speeds. To achieve high efficiency, simple, blocking caches are used. Such caches are not appropriate for processor designs such as Runahead and out-of-order execution that require nonblocking caches to tolerate main memory latencies. Instead, these processors use non-blocking caches to extract memory level parallelism and improve performance. However, conventional non-blocking cache designs are expensive and slow on FPGAs as they use content-addressable memories (CAMs). This work proposes NCOR, an FPGA-friendly non-blocking cache that exploits the key properties of Runahead execution. NCOR does not require CAMs and utilizes smart cache controllers. A 4 KB NCOR operates at 329 MHz on Stratix III FPGAs while it uses only 270 logic elements. A 32 KB NCOR operates at 278 Mhz and uses 269 logic elements.

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