Cache design for eliminating the address translation bottleneck and reducing the tag area cost

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.2002.1106791 ◽

2003 ◽

Author(s):

Yen-Jen Chang ◽

Feipei Lai ◽

Shanq-Jang Ruan

Keyword(s):

Address Translation ◽

Cache Design

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Early resolution of address translation in cache design

Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1990.130264 ◽

2002 ◽

Cited By ~ 12

Author(s):

K. Hua ◽

A. Hunt ◽

L. Liu ◽

J.-K. Peir ◽

D. Pruett ◽

...

Keyword(s):

Address Translation ◽

Cache Design

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TLB for Free: In-Cache Address Translation for a Multiprocessor Workstation

10.21236/ada611687 ◽

1985 ◽

Cited By ~ 4

Author(s):

Scott A. Ritchie

Keyword(s):

Address Translation

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A low energy cache design for multimedia applications exploiting set access locality

Journal of Systems Architecture ◽

10.1016/j.sysarc.2005.02.003 ◽

2005 ◽

Vol 51 (10-11) ◽

pp. 653-664 ◽

Cited By ~ 1

Author(s):

Jun Yang ◽

Jia Yu ◽

Youtao Zhang

Keyword(s):

Multimedia Applications ◽

Low Energy ◽

Cache Design

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Network Address Translation (NAT)

ACM SIGCOMM Computer Communication Review ◽

10.1145/2766330.2766340 ◽

2015 ◽

Vol 45 (2) ◽

pp. 50-50 ◽

Cited By ~ 1

Author(s):

Paul Francis

Keyword(s):

Network Address Translation ◽

Address Translation

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Architectural support for address translation on GPUs

ACM SIGPLAN Notices ◽

10.1145/2644865.2541942 ◽

2014 ◽

Vol 49 (4) ◽

pp. 743-758 ◽

Cited By ~ 4

Author(s):

Bharath Pichai ◽

Lisa Hsu ◽

Abhishek Bhattacharjee

Keyword(s):

Architectural Support ◽

Address Translation

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Architectural support for address translation on GPUs

ACM SIGARCH Computer Architecture News ◽

10.1145/2654822.2541942 ◽

2014 ◽

Vol 42 (1) ◽

pp. 743-758 ◽

Cited By ~ 5

Author(s):

Bharath Pichai ◽

Lisa Hsu ◽

Abhishek Bhattacharjee

Keyword(s):

Architectural Support ◽

Address Translation

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CARAT: a case for virtual memory through compiler- and runtime-based address translation

Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation ◽

10.1145/3385412.3385987 ◽

2020 ◽

Author(s):

Brian Suchy ◽

Simone Campanoni ◽

Nikos Hardavellas ◽

Peter Dinda

Keyword(s):

Virtual Memory ◽

Address Translation

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Address translation in telecommunication features

ACM Transactions on Software Engineering and Methodology ◽

10.1145/1005561.1005562 ◽

2004 ◽

Vol 13 (1) ◽

pp. 1-36 ◽

Cited By ~ 6

Author(s):

Pamela Zave

Keyword(s):

Address Translation

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A scheme for implementing address translation storage buffers

IEEE CCECE2002 Canadian Conference on Electrical and Computer Engineering Conference Proceedings (Cat No 02CH37373) CCECE-02 ◽

10.1109/ccece.2002.1013014 ◽

2003 ◽

Author(s):

A.H. Mohamed ◽

A. Sagahyroon

Keyword(s):

Address Translation

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Nonprime memory systems and error correction in address translation

IEEE Transactions on Computers ◽

10.1109/12.559804 ◽

1997 ◽

Vol 46 (1) ◽

pp. 75-79 ◽

Cited By ~ 1

Author(s):

R.S. Katti

Keyword(s):

Error Correction ◽

Memory Systems ◽

Address Translation

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