Nonprime memory systems and error correction in address translation

1997 ◽  
Vol 46 (1) ◽  
pp. 75-79 ◽  
Author(s):  
R.S. Katti
Keyword(s):  
Error Correction ◽  
Memory Systems ◽  
Address Translation

On the Use of Euclidean Geometry Codes for Efficient Multibit Error Correction on Memory Systems

2012 ◽  
Vol 59 (4) ◽  
pp. 824-828 ◽  
Author(s):  
Pedro Reviriego ◽  
Mark F. Flanagan ◽  
Shih-Fu Liu ◽  
Juan A. Maestro
Keyword(s):  
Error Correction ◽  
Euclidean Geometry ◽  
Memory Systems

SMusket: Spark-based DNA error correction on distributed-memory systems

2020 ◽  
Vol 111 ◽  
pp. 698-713 ◽  
Author(s):  
Roberto R. Expósito ◽  
Jorge González-Domínguez ◽  
Juan Touriño
Keyword(s):  
Error Correction ◽  
Distributed Memory ◽  
Memory Systems

Decoupled Address Translation for Heterogeneous Memory Systems

2020 ◽  
Author(s):  
Bokyeong Kim ◽  
Soojin Hwang ◽  
Sanghoon Cha ◽  
Chang Hyun Park ◽  
Jongse Park ◽  
...  
Keyword(s):  
Memory Systems ◽  
Address Translation

Compact and High-Speed Hsiao-Based SEC-DED Codec for Cache Memory

2021 ◽  
pp. 2250004
Author(s):  
Jagannath Samanta ◽  
Akash Kewat
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
High Speed ◽  
Memory Systems ◽  
Cache Memory ◽  
Error Correction Codes ◽  
Parity Check Matrix ◽  
Single Error ◽  
Check Matrix ◽  
Field Programmable

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev. 14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab. 73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability.

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