IBM single chip RISC processor (RSC)

2003 ◽  
Author(s):  
C.R. Moore ◽  
D.M. Balser ◽  
J.S. Muhich ◽  
R.E. East
Keyword(s):  
Single Chip ◽  
Risc Processor

Development of Image Recognition Processor Based on Configurable Processor

2005 ◽  
Vol 17 (4) ◽  
pp. 437-446 ◽  
Author(s):  
Takashi Miyamori ◽  
◽  
Jun Tanabe ◽  
Yasuhiro Taniguchi ◽  
Kenji Furukawa ◽  
...  
Keyword(s):  
Face Recognition ◽  
Image Recognition ◽  
Cmos Technology ◽  
Single Chip ◽  
Processor Core ◽  
Actual Application ◽  
Risc Processor ◽  
Execution Speed ◽  
Configurable Processor ◽  
Sdram Controller

We developed an image recognition processor, “Visconti,” based on a configurable processor. Three VLIW processors that execute three instructions in parallel are integrated into a single chip with peripheral modules such as video I/Os and an SDRAM controller. Each VLIW processor has a RISC processor core and a VLIW coprocessor dedicated to image processing. The coprocessor executes SIMD instructions such as 8-parallel byte. Visconti was fabricated using 0.13μm CMOS technology, operates at 150MHz, and consumes about 1W. We present actual application examples of Visconti, onboard surveillance for automobiles and face recognition. Compared to cases in which only the processor core is used, execution speed per one processor increases about 16 times for onboard surveillance and about five times per three processors for face recognition. These applications can be processed in real time.

Single chip dual-issue risc processor for real-time MPEG-2 software decoding

1999 ◽  
Vol 20 (6-7) ◽  
pp. 436-437
Author(s):  
Edgar Holmann ◽  
Toyohiko Yoshida ◽  
Akira Yamada ◽  
Shin-Ichi Uramoto
Keyword(s):  
Real Time ◽  
Single Chip ◽  
Risc Processor

A single-chip 802.11a MAC/PHY with a 32-b RISC processor

2003 ◽  
Vol 38 (11) ◽  
pp. 2001-2009 ◽  
Author(s):  
T. Fujisawa ◽  
Jun Hasegawa ◽  
K. Tsuchie ◽  
T. Shiozawa ◽  
T. Fujita ◽  
...  
Keyword(s):  
Single Chip ◽  
Risc Processor

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

DESIGN AND VERIFICATION OF 16-BIT RISC PROCESSOR USING SYSTEMVERILOG

2018 ◽  
Vol 6 (4) ◽  
pp. 38
Author(s):  
S. M. BHAGAT ◽  
S. U. BHANDARI ◽  
◽  
Keyword(s):  
Risc Processor

Research on highly parallel embedded control system design and implementation method

Impact ◽  
2019 ◽  
Vol 2019 (10) ◽  
pp. 44-46
Author(s):  
Masato Edahiro ◽  
Masaki Gondo
Keyword(s):  
Computer Architecture ◽  
Intelligent Systems ◽  
Large Scale ◽  
General Purpose ◽  
Heterogeneous Structure ◽  
Single Chip ◽  
Powertrain Control ◽  
Processing Power ◽  
Hardware Description ◽  
Many Core

The pace of technology's advancements is ever-increasing and intelligent systems, such as those found in robots and vehicles, have become larger and more complex. These intelligent systems have a heterogeneous structure, comprising a mixture of modules such as artificial intelligence (AI) and powertrain control modules that facilitate large-scale numerical calculation and real-time periodic processing functions. Information technology expert Professor Masato Edahiro, from the Graduate School of Informatics at the Nagoya University in Japan, explains that concurrent advances in semiconductor research have led to the miniaturisation of semiconductors, allowing a greater number of processors to be mounted on a single chip, increasing potential processing power. 'In addition to general-purpose processors such as CPUs, a mixture of multiple types of accelerators such as GPGPU and FPGA has evolved, producing a more complex and heterogeneous computer architecture,' he says. Edahiro and his partners have been working on the eMBP, a model-based parallelizer (MBP) that offers a mapping system as an efficient way of automatically generating parallel code for multi- and many-core systems. This ensures that once the hardware description is written, eMBP can bridge the gap between software and hardware to ensure that not only is an efficient ecosystem achieved for hardware vendors, but the need for different software vendors to adapt code for their particular platforms is also eliminated.

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