Development of Image Recognition Processor Based on Configurable Processor

2005 ◽  
Vol 17 (4) ◽  
pp. 437-446 ◽  
Author(s):  
Takashi Miyamori ◽  
◽  
Jun Tanabe ◽  
Yasuhiro Taniguchi ◽  
Kenji Furukawa ◽  
...  
Keyword(s):  
Face Recognition ◽  
Image Recognition ◽  
Cmos Technology ◽  
Single Chip ◽  
Processor Core ◽  
Actual Application ◽  
Risc Processor ◽  
Execution Speed ◽  
Configurable Processor ◽  
Sdram Controller

We developed an image recognition processor, “Visconti,” based on a configurable processor. Three VLIW processors that execute three instructions in parallel are integrated into a single chip with peripheral modules such as video I/Os and an SDRAM controller. Each VLIW processor has a RISC processor core and a VLIW coprocessor dedicated to image processing. The coprocessor executes SIMD instructions such as 8-parallel byte. Visconti was fabricated using 0.13μm CMOS technology, operates at 150MHz, and consumes about 1W. We present actual application examples of Visconti, onboard surveillance for automobiles and face recognition. Compared to cases in which only the processor core is used, execution speed per one processor increases about 16 times for onboard surveillance and about five times per three processors for face recognition. These applications can be processed in real time.

scholarly journals Energy challenges in optical access and aggregation networks

2016 ◽  
Vol 374 (2062) ◽  
pp. 20140435 ◽  
Author(s):  
Daniel C. Kilper ◽  
Houman Rastegarfar
Keyword(s):  
Optical Networks ◽  
Optical Switching ◽  
Energy Use ◽  
Future Internet ◽  
Critical Issue ◽  
Optical Systems ◽  
The Internet ◽  
Total System ◽  
Single Chip ◽  
Processor Core

Scalability is a critical issue for access and aggregation networks as they must support the growth in both the size of data capacity demands and the multiplicity of access points. The number of connected devices, the Internet of Things, is growing to the tens of billions. Prevailing communication paradigms are reaching physical limitations that make continued growth problematic. Challenges are emerging in electronic and optical systems and energy increasingly plays a central role. With the spectral efficiency of optical systems approaching the Shannon limit, increasing parallelism is required to support higher capacities. For electronic systems, as the density and speed increases, the total system energy, thermal density and energy per bit are moving into regimes that become impractical to support—for example requiring single-chip processor powers above the 100 W limit common today. We examine communication network scaling and energy use from the Internet core down to the computer processor core and consider implications for optical networks. Optical switching in data centres is identified as a potential model from which scalable access and aggregation networks for the future Internet, with the application of integrated photonic devices and intelligent hybrid networking, will emerge.

CMOS PULSE GENERATOR FOR BPSK, OOK, PAM, AND PPM MODULATIONS

2009 ◽  
Vol 18 (03) ◽  
pp. 487-495 ◽  
Author(s):  
VINCENZO STORNELLI ◽  
GIUSEPPE FERRI ◽  
KING PACE
Keyword(s):  
Remote Control ◽  
Power Consumption ◽  
Pulse Duration ◽  
Short Range ◽  
Pulse Generator ◽  
Supply Voltage ◽  
Pulse Repetition Frequency ◽  
Cmos Technology ◽  
Single Chip ◽  
Control Applications

This work presents a single chip integrated pulse generator-modulator to be utilized in a short range wireless radio sensors remote control applications. The circuit, which can generate single pulses, modulated in BPSK, OOK, PAM, and also PPM, has been developed in a standard CMOS technology (AMS 0.35 μm). Typical pulse duration is about 1 ns while pulse repetition frequency is until 200 MHz (5 ns "chip" time). The operating supply voltage is ± 2.5 V, while the whole power consumption is about 15 mW. Post-layout parametric and corner analyses have confirmed the theoretical expectations.

Remote Diagnosis Method of Substation Equipment Fault Based on Image Recognition Technology

2021 ◽  
Author(s):  
Pei Zhang ◽  
Wenshuai Hu ◽  
Xiaolong Hao ◽  
Dingding Xi ◽  
Shuaishuai Yan
Keyword(s):  
Fault Diagnosis ◽  
Image Recognition ◽  
Remote Diagnosis ◽  
Application Process ◽  
Equipment Operation ◽  
Actual Application ◽  
Accurate Detection ◽  
Diagnosis Method ◽  
Substation Equipment ◽  
Information Characteristics

In order to better guarantee the operation effect of substation equipment, a remote fault diagnosis method of substation equipment based on image recognition technology is proposed. Combined with image recognition technology, the running image of substation equipment is tracked and collected, the information characteristics of substation equipment are deeply excavated, and the fault area of substation equipment is accurately judged. Remote positioning has been carried out to realize the accurate detection of substation equipment fault. Finally, through the experiment, the remote diagnosis method of substation equipment fault based on image recognition technology is in the actual application process With higher accuracy, it can effectively ensure the safety of substation equipment operation.

Design of an L1 band low noise single-chip GPS receiver in 0.18 μ m CMOS technology

2010 ◽  
Vol 17 (3) ◽  
pp. 60-65 ◽  
Author(s):  
Ying-mei CHEN ◽  
Zhi-qun LI ◽  
Zhi-gong WANG ◽  
Yong-kang JING ◽  
Li ZHANG
Keyword(s):  
Cmos Technology ◽  
Low Noise ◽  
Gps Receiver ◽  
Single Chip

Package Voltage Regulators: The Answer for Power Management Challenges

2019 ◽  
Vol 2019 (1) ◽  
pp. 000438-000443 ◽  
Author(s):  
Joseph Meyer ◽  
Reza Moghimi ◽  
Noah Sturcken
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Power Conversion ◽  
Cmos Technology ◽  
Voltage Regulation ◽  
Voltage Regulators ◽  
Electronic Systems ◽  
Single Chip ◽  
Fully Integrated ◽  
Computational Performance

Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.

scholarly journals Fabrication of a CMOS-based Imaging Chip with Monolithically Integrated RGB and NIR Filters

Proceedings ◽  
2019 ◽  
Vol 2 (13) ◽  
pp. 751
Author(s):  
Bart Vereecke ◽  
Els Van Besien ◽  
Deniz Sabuncuoglu Tezcan ◽  
Nick Spooren ◽  
Nicolaas Tack ◽  
...  
Keyword(s):  
Bandpass Filter ◽  
Imaging System ◽  
Low Cost ◽  
Cmos Technology ◽  
Image Sensors ◽  
Single Chip ◽  
Interference Filters ◽  
Monolithically Integrated ◽  
Recent Developments

Recent developments in multispectral cameras have demonstrated how compact and low-cost spectral sensors can be made by monolithically integrating filters on top of commercially available image sensors. In this paper, the fabrication of a RGB + NIR variation to such a single-chip imaging system is described, including the integration of a metallic shield to minimize crosstalk, and two interference filters: a NIR blocking filter, and a NIR bandpass filter. This is then combined with standard polymer based RGB colour filters. Fabrication of this chip is done in imec’s 200 mm cleanroom using standard CMOS technology, except for the addition of RGB colour filters and microlenses, which is outsourced.

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