A reduced complexity implementation of the Log-Map algorithm for turbo-codes decoding

2002 ◽  
Author(s):  
Yan Wang ◽  
Chi-Ying Tsui ◽  
R.S.K. Cheng
Keyword(s):  
Turbo Codes ◽  
Map Algorithm ◽  
Reduced Complexity ◽  
Log Map

scholarly journals Efficient MAP-algorithm implementation on programmable architectures

2003 ◽  
Vol 1 ◽  
pp. 259-263 ◽  
Author(s):  
F. Kienle ◽  
H. Michel ◽  
F. Gilbert ◽  
N. Wehn
Keyword(s):  
Turbo Codes ◽  
Communication Systems ◽  
Building Blocks ◽  
Communication Performance ◽  
Channel Decoding ◽  
Turbo Decoder ◽  
Decoding Algorithms ◽  
Map Algorithm ◽  
Algorithm Implementation ◽  
Log Map

Abstract. Maximum-A-Posteriori (MAP) decoding algorithms are important HW/SW building blocks in advanced communication systems due to their ability to provide soft-output informations which can be efficiently exploited in iterative channel decoding schemes like Turbo-Codes. Multi-standards demand flexible implementations on programmable platforms. In this paper we analyze a quantized turbo-decoder based on a Max-Log-MAP algorithm with Extrinsic Scaling Factor (ESF). Its communication performance approximate to a Turbo-Decoder with a Log-MAP algorithm and is less sensitive to quantization effects. We present Turbo-Decoder implementations on state-of-the-art DSPs and show that only a Max-Log-MAP implementation fulfills a throughput requirement of ~2 Mbit/s. The negligible overhead for the ESF implementation strengthen the use of Max-Log-MAP with ESF implementation on programmable platforms.

Reduced complexity per-survivor iterative timing recovery using max-log-MAP algorithm

2020 ◽  
Vol 17 (2) ◽  
pp. 146
Author(s):  
Mau Luen Tham ◽  
Chuan Hsian Pu ◽  
Ezra Morris Abraham Gnanamuthu ◽  
Fook Loong Lo
Keyword(s):  
Timing Recovery ◽  
Map Algorithm ◽  
Reduced Complexity ◽  
Log Map

Reduced complexity per-survivor iterative timing recovery using max-log-MAP algorithm

2020 ◽  
Vol 17 (2) ◽  
pp. 146
Author(s):  
Chuan Hsian Pu ◽  
Ezra Morris Abraham Gnanamuthu ◽  
Fook ong Lo ◽  
Mau Luen Tham
Keyword(s):  
Timing Recovery ◽  
Map Algorithm ◽  
Reduced Complexity ◽  
Log Map

An Improved Log-MAP Algorithm For BICM-ID Embedded Turbo Codes

2013 ◽  
Vol 433-435 ◽  
pp. 634-638
Author(s):  
Jian Wang ◽  
Jian Ping Li
Keyword(s):  
Turbo Codes ◽  
Iterative Decoding ◽  
Optimal Algorithm ◽  
Linear Interpolation ◽  
Coded Modulation ◽  
Logarithmic Correction ◽  
Map Algorithm ◽  
Lower Complexity ◽  
Performance Gains ◽  
Log Map

This paper presents a novel decoding algorithm for bit-interleaved coded modulation iterative decoding (BICM-ID) embedded turbo codes. It can yield good bit error rate (BER) performance with much lower complexity. The improved algorithm exploits a linear interpolation and optimal mean square approximation function to replace the logarithmic correction in the Jacobian logarithmic function based on the MacLaurin Series, which avoids complicated logarithm look-up table operations in Log-MAP. Simulation results show that the novel algorithm obtains can offer almost equivalent performance to the optimal algorithm. Compared with the improved MAX-Log-MAP algorithm, the proposed algorithm can reduce about 34% of computational complexity, meanwhile it achieves 0.1db-0.16db performance gains.

Research and Realization by FPGA of Turbo Codes

2012 ◽  
Vol 588-589 ◽  
pp. 765-768
Author(s):  
Jin Xu ◽  
Ying Zhao ◽  
Shu Qiang Duan
Keyword(s):  
Turbo Codes ◽  
Channel Coding ◽  
Turbo Code ◽  
Noise Signal ◽  
Low Noise ◽  
Random Coding ◽  
Map Algorithm ◽  
Key Issues ◽  
Turbo Encoder ◽  
Log Map

Turbo Code is a channel coding with excellent error-correcting performance in the condition of low noise-signal ratio.It has a superior decoding performance approaching the Shannon limit by adopting the random coding and decoding. This paper focuses on Turbo code and its implementation with FPGA and deeply analyzes the decoding theory and algorithm of Turbo code. Firstly, it analyzes the decoding theory of Turbo code. Then, it discusses key issues in the process of implementation with the most excellent and complicated Max—log—MAP algorithm. At last, it ends up with the Turbo encoder and decoding algorithm which hardware is successfully implemented finally.

A Literature Survey on Algorithms and Hardware Architectures of Max-Log-MAP Demapping

2021 ◽  
pp. 2230001
Author(s):  
Mostafa Rizk ◽  
Amer Baghdadi ◽  
Michel Jézéquel
Keyword(s):  
Research Effort ◽  
High Order ◽  
Performance Criteria ◽  
Hardware Complexity ◽  
Map Algorithm ◽  
Resource Requirements ◽  
Hardware Resource ◽  
Modulation Schemes ◽  
And Performance ◽  
Log Map

Emergent wireless communication standards, which are employed in different transmission environments, support various modulation schemes. High-order constellations are targeted to achieve high bandwidth efficiency. However, the complexity of the symbol-by-symbol Maximum A Posteriori (MAP) algorithm increases dramatically for these high-order modulation schemes. In order to reduce the hardware complexity, the suboptimal Max-Log-MAP, which is the direct transformation of the MAP algorithm into logarithmic domain, is alternatively implemented. In the literature, a great deal of research effort has been invested into Max-Log-MAP demapping. Several simplifications are presented to meet with specific constellations. In addition, the hardware implementations dedicated for Max-Log-MAP demapping vary greatly in terms of design choices, supported flexibility and performance criteria, making them a challenge to compare. This paper explores the published Max-Log-MAP algorithm simplifications and existing hardware demapper designs and presents an extensive review of the current literature. In-depth comparisons are drawn amongst the designs and different key performance characteristics are described, namely, achieved throughput, hardware resource requirements and flexibility. This survey should facilitate fair comparisons of future designs, as well as opportunities for improving the design of Max-Log-MAP demappers.

scholarly journals Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

2014 ◽  
Vol 63 (3) ◽  
pp. 531-537 ◽  
Author(s):  
Maurizio Martina ◽  
Stylianos Papaharalabos ◽  
P. Takis Mathiopoulos ◽  
Guido Masera
Keyword(s):  
Low Complexity ◽  
Turbo Decoder ◽  
Map Algorithm ◽  
Hardware Architectures ◽  
Log Map
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