Performance evaluation of a Turbo Codec with Log-MAP algorithm on FPGA and CPU

2011 ◽  
Author(s):  
Hector Ivan Reyes Moncayo ◽  
Naima Kaabouch ◽  
Wen-Chen Hu ◽  
Anlei Wang
Keyword(s):  
Performance Evaluation ◽  
Map Algorithm ◽  
Log Map

A Literature Survey on Algorithms and Hardware Architectures of Max-Log-MAP Demapping

2021 ◽  
pp. 2230001
Author(s):  
Mostafa Rizk ◽  
Amer Baghdadi ◽  
Michel Jézéquel
Keyword(s):  
Research Effort ◽  
High Order ◽  
Performance Criteria ◽  
Hardware Complexity ◽  
Map Algorithm ◽  
Resource Requirements ◽  
Hardware Resource ◽  
Modulation Schemes ◽  
And Performance ◽  
Log Map

Emergent wireless communication standards, which are employed in different transmission environments, support various modulation schemes. High-order constellations are targeted to achieve high bandwidth efficiency. However, the complexity of the symbol-by-symbol Maximum A Posteriori (MAP) algorithm increases dramatically for these high-order modulation schemes. In order to reduce the hardware complexity, the suboptimal Max-Log-MAP, which is the direct transformation of the MAP algorithm into logarithmic domain, is alternatively implemented. In the literature, a great deal of research effort has been invested into Max-Log-MAP demapping. Several simplifications are presented to meet with specific constellations. In addition, the hardware implementations dedicated for Max-Log-MAP demapping vary greatly in terms of design choices, supported flexibility and performance criteria, making them a challenge to compare. This paper explores the published Max-Log-MAP algorithm simplifications and existing hardware demapper designs and presents an extensive review of the current literature. In-depth comparisons are drawn amongst the designs and different key performance characteristics are described, namely, achieved throughput, hardware resource requirements and flexibility. This survey should facilitate fair comparisons of future designs, as well as opportunities for improving the design of Max-Log-MAP demappers.

scholarly journals Efficient MAP-algorithm implementation on programmable architectures

2003 ◽  
Vol 1 ◽  
pp. 259-263 ◽  
Author(s):  
F. Kienle ◽  
H. Michel ◽  
F. Gilbert ◽  
N. Wehn
Keyword(s):  
Turbo Codes ◽  
Communication Systems ◽  
Building Blocks ◽  
Communication Performance ◽  
Channel Decoding ◽  
Turbo Decoder ◽  
Decoding Algorithms ◽  
Map Algorithm ◽  
Algorithm Implementation ◽  
Log Map

Abstract. Maximum-A-Posteriori (MAP) decoding algorithms are important HW/SW building blocks in advanced communication systems due to their ability to provide soft-output informations which can be efficiently exploited in iterative channel decoding schemes like Turbo-Codes. Multi-standards demand flexible implementations on programmable platforms. In this paper we analyze a quantized turbo-decoder based on a Max-Log-MAP algorithm with Extrinsic Scaling Factor (ESF). Its communication performance approximate to a Turbo-Decoder with a Log-MAP algorithm and is less sensitive to quantization effects. We present Turbo-Decoder implementations on state-of-the-art DSPs and show that only a Max-Log-MAP implementation fulfills a throughput requirement of ~2 Mbit/s. The negligible overhead for the ESF implementation strengthen the use of Max-Log-MAP with ESF implementation on programmable platforms.

scholarly journals Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

2014 ◽  
Vol 63 (3) ◽  
pp. 531-537 ◽  
Author(s):  
Maurizio Martina ◽  
Stylianos Papaharalabos ◽  
P. Takis Mathiopoulos ◽  
Guido Masera
Keyword(s):  
Low Complexity ◽  
Turbo Decoder ◽  
Map Algorithm ◽  
Hardware Architectures ◽  
Log Map

Reduced complexity per-survivor iterative timing recovery using max-log-MAP algorithm

2020 ◽  
Vol 17 (2) ◽  
pp. 146
Author(s):  
Mau Luen Tham ◽  
Chuan Hsian Pu ◽  
Ezra Morris Abraham Gnanamuthu ◽  
Fook Loong Lo
Keyword(s):  
Timing Recovery ◽  
Map Algorithm ◽  
Reduced Complexity ◽  
Log Map
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