DUO: Exposing On-Chip Redundancy to Rank-Level ECC for High Reliability

2018 ◽  
Author(s):  
Seong-Lyong Gong ◽  
Jungrae Kim ◽  
Sangkug Lym ◽  
Michael Sullivan ◽  
Howard David ◽  
...  
Keyword(s):  
High Reliability ◽  
On Chip

Reflow Process Simulation for Dispersion Evaluation of Solder Joint Shape on Chip Component

2009 ◽  
Author(s):  
Kanji Takagi ◽  
Qiang Yu ◽  
Tadahiro Shibutani ◽  
Hiroki Miyauchi
Keyword(s):  
Surface Tension ◽  
Solder Joint ◽  
High Reliability ◽  
Electronic Components ◽  
Reflow Process ◽  
Solder Joint Reliability ◽  
Automotive Electronic ◽  
Joint Reliability ◽  
On Chip ◽  
Joint Shape

The miniaturization and high reliability for automotive electronic components has been strongly requested. Generally, electronic component and printed wiring board are connected using solder joint. The reliability of solder joint has widely dispersion. For the dispersion reduction of solder joint reliability, not only design factors but manufacturing factors should be optimized. The evaluation of manufacturing factors for solder joint reliability was very difficult by experimental evaluation alone. Therefore, the reflow process simulation was established. The simulation was reenacted soldering process on chip component, which was the most severe reliability in automotive electronic components. The novelty of simulation was the coupled analysis of flow and rigid for simulating self-alignment of chip component. In this simulation, contact angle and surface tension was very important factor. So, these characteristics were measured based on Spread test and Wetting balance tests using the specimens. In the result, the solder joint shape of analysis was agree with the one of specimens using the measured contact angle and surface tension. Next, the effect of manufacturing process dispersion for solder joint shape was evaluated. The factors were mount offset and length unbalance of electrodes on chip component. As a result, the mount offset was not affected solder joint shape of chip component until a certain level. Also, the unbalance of electrode of chip component was not almost affected for solder joint shape of chip component because a part was moved to the center of part by surface tension of solder joint. Finally, the relation between the estimated solder joint shape and fatigue life of solder joints is evaluated using crack propagation analysis based on Manson-Coffin’s law and Miner’s rule. When the value of mount offset was large, the crack propagation mode was changed and the fatigue life of solder joint was decreased. As mentioned above, it was able to evaluate the relation between manufacturing factors and solder joint reliability. Accordingly, this simulation was very useful for consideration on the miniaturization, high reliability and appropriate margin for design of electronic components.

Direct On-Chip 3-D Aerosol Jet Printing With High Reliability

2017 ◽  
Vol 7 (8) ◽  
pp. 1369-1376 ◽  
Author(s):  
Xing Lan ◽  
Xuejun Lu ◽  
Maggie Yihong Chen ◽  
Dan Scherrer ◽  
Thomas Chung ◽  
...  
Keyword(s):  
High Reliability ◽  
Jet Printing ◽  
On Chip ◽  
Aerosol Jet Printing

Simulation and Design of a Cell-Based Digital Microfluidic Chip for Continuous Monitoring of Acute Toxic Chemicals

2013 ◽  
Vol 336-338 ◽  
pp. 523-527
Author(s):  
Tao Dong ◽  
Matteo Molino ◽  
Danilo Demarchi
Keyword(s):  
Vibrio Fischeri ◽  
High Reliability ◽  
Water Environment ◽  
Disperse Medium ◽  
Experimental Investigations ◽  
Droplet Generator ◽  
Lab On Chip ◽  
High Efficient ◽  
On Chip ◽  
Digital Microfluidic

In this study, a lab-on-chip (LOC) system is designed for the cell sensors to provide a high-efficient continuous analysis platform of acute toxicants in water environment. The chip is composed of three domains, including counter-flow micromixers, a T-junction droplet generator and time delay channels (TD-Cs). Water sample and bioluminescent bacterium Vibrio Fischeri (VF) are imported into the micromixers before that the droplet generator encapsulates them inside aqueous droplets separated by air. Air flow is the disperse medium, which can guarantee sufficient oxygen supply for the cells in droplets. The system shows high reliability and stability through numerical and experimental investigations.

scholarly journals Lightweight Cryptography for Network-on-Chip Data Encryption

2021 ◽  
Vol 2021 ◽  
pp. 1-10
Author(s):  
Riadh Ayachi ◽  
Ayoub Mhaouch ◽  
Abdessalem Ben Abdelali
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Network Performance ◽  
High Reliability ◽  
Data Encryption ◽  
Network On Chip ◽  
Security Problem ◽  
Finite State ◽  
On Chip ◽  
Main Component

System-on-chip (SoC) is the main processor for most recent applications such as the Internet of things (IoT). SoCs are composed of multiple blocks that communicate with each other through an integrated router. Data routing from a block to another poses many challenges. The network-on-chip (NoC) was used for the transmission of data from a source to a destination with high reliability, high speed, low power consumption, and low hardware occupation. An NoC is composed of a router, network links (NL), and network interface (NI). The main component of the NoC, the NI, is composed of an input/output FIFO, a finite state machine (FSM), pack, and depack modules. Data transmission from a block to another poses a security problem such as secret information extraction. In this paper, we proposed a data encryption framework for NoC based on a light encryption device (LED) algorithm. The main advantages of the proposed algorithm are to reduce the implementation area and to achieve high speed while reducing the power consumption. The proposed encryption framework was simulated Verilog/VHDL on the Xilinx ISE and implemented on the Xilinx Virtex 5 XC5VFX200T. The obtained results have shown that the proposed framework has a smaller area and higher speed compared to existing works. The proposed algorithm has reduced the NI implementation area and enhanced the network performance in terms of speed and security.

Reducing the number of passing links in the 2D-NoC for performance and reliability improvement

2020 ◽  
Vol 17 (5) ◽  
pp. 621-632
Author(s):  
Seyyed Javad Seyyed Mahdavi Chabok ◽  
Seyed Amin Alavi
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Network Reliability ◽  
Telecommunication Network ◽  
High Reliability ◽  
Routing Algorithm ◽  
Network Size ◽  
Content Type ◽  
Probability Of Collision ◽  
On Chip

Purpose The routing algorithm is one of the most important components in designing a network-on-chip (NoC). An effective routing algorithm can cause better performance and throughput, and thus, have less latency, lower power consumption and high reliability. Considering the high scalability in networks and fault occurrence on links, the more the packet reaches the destination (i.e. to cross the number of fewer links), the less the loss of packets and information would be. Accordingly, the proposed algorithm is based on reducing the number of passed links to reach the destination. Design/methodology/approach This paper presents a high-performance NoC that increases telecommunication network reliability by passing fewer links to destination. A large NoC is divided into small districts with central routers. In such a system, routing in large routes is performed through these central routers district by district. Findings By reducing the number of links, the number of routers also decreases. As a result, the power consumption is reduced, the performance of the NoC is improved, and the probability of collision with a faulty link and network latency is decreased. Originality/value The simulation is performed using the Noxim simulator because of its ability to manage and inject faults. The proposed algorithm, XY routing, as a conventional algorithm for the NoC, was simulated in a 14 × 14 network size, as the typical network size in the recent works.

Designing Thermally Uniform Mems Hot Micro-Bolometers

2002 ◽  
Vol 729 ◽  
Author(s):  
Nicholas Moelders ◽  
Martin U. Pralle ◽  
Mark P. McNeal ◽  
Irina Puscasu ◽  
Lisa Last ◽  
...  
Keyword(s):  
High Reliability ◽  
Chemical Species ◽  
Infrared Camera ◽  
Optical Power ◽  
Optical Emission ◽  
Sensor Chip ◽  
Optical Noise ◽  
Chip Design ◽  
Reliable Performance ◽  
On Chip

AbstractHere we describe the evolution of a silicon, MEMS-based chip design developed for infrared gas and chemical detection. The “Sensor-Chip,” with integrated photonic crystal and reflective optics, employs narrow-band optical emission/absorption for selective identification of gas and chemical species. Gas concentration is derived from attenuated optical power, which results in a change in device set point. This change in temperature results in a change in device resistance, via the TCR of the Si. Thermal non-uniformity across the device results in optical “noise” and accelerates localized thermal and electrical failures. This paper reports the influence of processing and design, on achieving uniformly heated, high reliability devices. Specifically, we examine the role of contacts, drive scheme, and device thermal distribution on chip design. Experimentally the temperature uniformity was characterized using an infrared camera. Experimental results indicate that the design of the contact areas in combination with the device design is essential for the reliable performance of the Sensor-Chip. Redesigned devices were fabricated and demonstrated as highly-selective gas and chemical sensors.

The Package Becomes the System

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-36
Author(s):  
Bruce J. Barbara
Keyword(s):  
High Reliability ◽  
Electrical Performance ◽  
Entire System ◽  
Single System ◽  
Wafer Level ◽  
Electromechanical Systems ◽  
Thermal Structures ◽  
On Chip ◽  
3D Stacking ◽  
System Miniaturization

The benefits of system miniaturization lower-cost, higher electrical performance and better thermal mechanical reliability, than the current approach of discrete component packaging have been discussed at length. Several technologies have been used to address these benefits. SOC, SiP, Fan-In and Fan Out and wafer level packages. Recently there has been much discussion about Fan Out Wafer Level packaging (FOWLP) to integrate the entire system in package. However, actual implementations fall short of a complete system in a package in that only few of the chips and some passives are currently integrated into the FOWLP. But what about the rest of the system? A true system also requires additional components not traditionally considered integrate-able into a package. These include antennas, batteries, thermal structures, RF, Optical, micro-electromechanical systems (MEMs), and micro sensor functions. The current FOWLP package technology as discussed by the media falls short of this type of system integration due to limitations in the number of chips that can be integrated and the lack of sufficient interconnect layers to support these functions in a system. 3D stacking has also been employed to improve the SiP by adding memory components. These implementations are limited to stacking of identical chips with through hole silicon vias (TSV) located remotely from any circuitry. Aurora Semiconductor will introduce a packaging technology where the package becomes the system. We call this technology 4DHSiP™ or 4D Heterogeneous System in package. 4DHSiP™ is a system miniaturization technology in contrast to system on chip (SOC) at the integrated circuit level and system in package stacked ICs and packages (SIP) at the module level. 4DHSiP™ is considered an inclusive system technology in which, SIP, thermal structures and batteries are considered as substantive technologies. 3D stacking is no longer limited by the location of the TSV within the stacked components. Heterogeneous multi-chip sub module layers can be stacked to accommodate additional system components. These layers, when interconnected, form the entire system. By stacking sub module layers, specific component types can be located on the top most layer as needed by specific function (e.g. Bio functions, Optical functions, Antennas). An example of this type of module stacking used to create an optical based system will be shown.4DHSiP™ is a new, emerging system concept where the device, package, and system board are miniaturized into a single system package including all the needed system functions. Such a single system package with multiple heterogeneous ICs provides all the system functions by co-design and fabrication of digital, radiofrequency (RF), optical, micro-electromechanical systems (MEMS) in either the IC or the system package. 4DHSiP™ combines the best on chip and off chip integration technologies to develop ultra-miniaturized, high-performance, multifunctional products. A significant benefit of this miniaturization is the elimination of multiple sockets and connectors currently used to connect sub-systems together. This ultra-miniaturization of multiple to mega functions, ultrahigh performance, low cost and high reliability will be the way systems are designed in the future to achieve More than Moore.

scholarly journals NoCGuard: A Reliable Network-on-Chip Router Architecture

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 342 ◽  
Author(s):  
Muhammad Akmal Shafique ◽  
Naveed Khan Baloch ◽  
Muhammad Iram Baig ◽  
Fawad Hussain ◽  
Yousaf Bin Zikria ◽  
...  
Keyword(s):  
Network Architecture ◽  
Fault Tolerant ◽  
Channel Allocation ◽  
High Reliability ◽  
Low Cost ◽  
Network On Chip ◽  
Time To Failure ◽  
Protection Factor ◽  
Router Architecture ◽  
On Chip

Aggressive scaling in deep nanometer technology enables chip multiprocessor design facilitated by the communication-centric architecture provided by Network-on-Chip (NoC). At the same time, it brings considerable challenges in reliability because a fault in the network architecture severely impacts the performance of a system. To deal with these reliability challenges, this research proposed NoCGuard, a reconfigurable architecture designed to tolerate multiple permanent faults in each pipeline stage of the generic router. NoCGuard router architecture uses four highly reliable and low-cost fault-tolerant strategies. We exploited resource borrowing and double routing strategy for the routing computation stage, default winner strategy for the virtual channel allocation stage, runtime arbiter selection and default winner strategy for the switch allocation stage and multiple secondary bypass paths strategy for the crossbar stage. Unlike existing reliable router architectures, our architecture features less redundancy, more fault tolerance, and high reliability. Reliability comparison using Mean Time to Failure (MTTF) metric shows 5.53-time improvement in a lifetime and using Silicon Protection Factor (SPF), 22-time improvement, which is better than state-of-the-art reliable router architectures. Synthesis results using 15 nm and 45 nm technology library show that additional circuitry incurs an area overhead of 28.7% and 28% respectively. Latency analysis using synthetic, PARSEC and SPLASH-2 traffic shows minor increase in performance by 3.41%, 12% and 15% respectively while providing high reliability.

A new architecture for online error detection and isolation in network on chip

2020 ◽  
Vol 26 (4) ◽  
pp. 307-323
Author(s):  
Chakib Nehnouh
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
High Reliability ◽  
Low Cost ◽  
Network On Chip ◽  
Fault Detection And Isolation ◽  
Main Concern ◽  
Transient Faults ◽  
Protection Factor ◽  
On Chip

The Network-on-Chip (NoC) has become a promising communication infrastructure for Multiprocessors-System-on-Chip (MPSoC). Reliability is a main concern in NoC and performance is degraded when NoC is susceptible to faults. A fault can be determined as a cause of deviation from the desired operation of the system (error). To deal with these reliability challenges, this work propose OFDIM (Online Fault Detection and Isolation Mechanism),a novel combined methodology to tolerate multiple permanent and transient faults. The new router architecture uses two modules to assure highly reliable and low-cost fault-tolerant strategy. In contrast to existing works, our architecture presents less area, more fault tolerance, and high reliability. The reliability comparison using Silicon Protection Factor (SPF), shows 22-time improvement and that additional circuitry incurs an area overhead of 27%, which is better than state-of-the-art reliable router architectures. Also, the results show that the throughput decreases only by 5.19% and minor increase in average latency 2.40% while providing high reliability.

AFRM: Adaptive and Fault-Tolerant Routing Method for 2D Network-on-Chip

2017 ◽  
Vol 26 (12) ◽  
pp. 1750200 ◽  
Author(s):  
Ruilian Xie ◽  
Jueping Cai ◽  
Peng Wang ◽  
Xin Zhang ◽  
Juan Wang
Keyword(s):  
Fault Tolerant ◽  
State Of The Art ◽  
High Reliability ◽  
Network Simulation ◽  
Network On Chip ◽  
Virtual Channels ◽  
Routing Method ◽  
Simulation Results ◽  
On Chip ◽  
2D Network

High reliability against undesirable effects is one of the key objectives in the design for Network-on-Chip (NoC). As a result, designing reliable and efficient routing method is highly desirable. This paper presents a novel turn model called NMad-y using one and two virtual channels along the [Formula: see text]- and [Formula: see text]-dimensions, respectively, and Adaptive and Fault-tolerant Routing Method (AFRM) which is designed based on the NMad-y turn model. AFRM can effectively tolerate multiple faulty routers and links in more complicated faulty situations by the link status of neighbor routers within two hops. AFRM is able to impose the reliability of network without losing the performance of network. Simulation results show that AFRM achieves better saturation throughput (0.83% on average) than a state-of-the-art fault-tolerant routing method and maintains high reliability of more than 97.43% on average.

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