scholarly journals Lightweight Cryptography for Network-on-Chip Data Encryption

2021 ◽  
Vol 2021 ◽  
pp. 1-10
Author(s):  
Riadh Ayachi ◽  
Ayoub Mhaouch ◽  
Abdessalem Ben Abdelali
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Network Performance ◽  
High Reliability ◽  
Data Encryption ◽  
Network On Chip ◽  
Security Problem ◽  
Finite State ◽  
On Chip ◽  
Main Component

System-on-chip (SoC) is the main processor for most recent applications such as the Internet of things (IoT). SoCs are composed of multiple blocks that communicate with each other through an integrated router. Data routing from a block to another poses many challenges. The network-on-chip (NoC) was used for the transmission of data from a source to a destination with high reliability, high speed, low power consumption, and low hardware occupation. An NoC is composed of a router, network links (NL), and network interface (NI). The main component of the NoC, the NI, is composed of an input/output FIFO, a finite state machine (FSM), pack, and depack modules. Data transmission from a block to another poses a security problem such as secret information extraction. In this paper, we proposed a data encryption framework for NoC based on a light encryption device (LED) algorithm. The main advantages of the proposed algorithm are to reduce the implementation area and to achieve high speed while reducing the power consumption. The proposed encryption framework was simulated Verilog/VHDL on the Xilinx ISE and implemented on the Xilinx Virtex 5 XC5VFX200T. The obtained results have shown that the proposed framework has a smaller area and higher speed compared to existing works. The proposed algorithm has reduced the NI implementation area and enhanced the network performance in terms of speed and security.

scholarly journals Detection and Monitoring Intra/Inter Crosstalk in Optical Network on Chip

2018 ◽  
Vol 8 (6) ◽  
pp. 4912
Author(s):  
Ahmed Jedidi
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Data Exchange ◽  
High Reliability ◽  
Optical Network ◽  
Network On Chip ◽  
Computer Applications ◽  
Multiprocessor System ◽  
Crosstalk Noise ◽  
On Chip

Multiprocessor system-on-chip (MPSoC) has become an attractive solution for improving the performance of single chip in objective to satisfy the performance growing exponentially of the computer applications as multimedia applications. However, the communication between the different processors’ cores presents the first challenge front the high performance of MPSoC. Besides, Network on Chip (NoC) is among the most prominent solution for handling the on-chip communication. Besides, NoC potential limited by physical limitation, power consumption, latency and bandwidth in the both case: increasing data exchange or scalability of Multicores. Optical communication offers a wider bandwidth and lower power consumption, based on, a new technology named Optical Network-on-Chip (ONoC) has been introduced in MPSoC. However, ONoC components induce the crosstalk noise in the network on both forms intra/inter crosstalk. This serious problem deteriorates the quality of signals and degrades network performance. As a result, detection and monitoring the impairments becoming a challenge to keep the performance in the ONoC. In this article, we propose a new system to detect and monitor the crosstalk noise in ONoC. Particularly, we present an analytic model of intra/inter crosstalk at the optical devices. Then, we evaluate these impairments in objective to present the motivation to detect and monitor crosstalk in ONoC, in which our system has the capability to detect, to localize, and to monitor the crosstalk noise in the whole network. This system offers high reliability, scalability and efficiency with time running time less than 20 ms.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

Network-on-Chip for Low Power MAP Decoder Using Folded Technique and CORDIC Algorithm for 5G Network

2021 ◽  
pp. 96-108
Author(s):  
Shiyamala S. ◽  
Vijay Soorya J. ◽  
Sanjay P. S. ◽  
Sathappan K.
Keyword(s):  
Turbo Codes ◽  
High Speed ◽  
Life Time ◽  
Full Adder ◽  
Network On Chip ◽  
Cordic Algorithm ◽  
Effective Manner ◽  
Constraint Length ◽  
On Chip ◽  
Map Decoder

With different constraint length (K), time scale, and code rate, modified MAP (maximum a posteriori) decoder architecture using folding technique, which has a linear life time chart, is developed, and dedicated turbo codes will be placed in a network-on-chip for various wireless applications. Folded techniques mitigated the number of latches used in interleaving and deinterleaving unit by adopting forward and backward resource utilizing method to M-2, where M is the number of rows and end-to-end delay get reduced to 2M. By replacing conventional full adder by high speed adder using 2 x 1 multiplexer to calculate the forward state metrics and reverse state metrics will minimize the power consumption utilization in an effective manner. In s similar way, CORDIC (Coordinated ROtation DIgital Computer) algorithm is used to calculate the LLR value and confer a highly precise value with less computational complexity by means of only shifting and adding methods.

Dual Monitoring Communication for Self-Aware Network-on-Chip

2012 ◽  
Vol 3 (3) ◽  
pp. 72-91
Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Cmos Technology ◽  
Network On Chip ◽  
Time Profile ◽  
Self Awareness ◽  
Monitoring Networks ◽  
Communication Architecture ◽  
Run Time ◽  
On Chip

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

scholarly journals Congestion-aware wireless network-on-chip for high-speed communication

Automatika ◽  
2019 ◽  
Vol 61 (1) ◽  
pp. 92-98
Author(s):  
M. Devanathan ◽  
V. Ranganathan ◽  
P. Sivakumar
Keyword(s):  
Wireless Network ◽  
High Speed ◽  
Network On Chip ◽  
On Chip ◽  
Congestion Aware

High Speed Low Power Ping Pong Buffering Based Network Interface for Network on Chip

2013 ◽  
Vol 9 (3) ◽  
pp. 322-331 ◽  
Author(s):  
K. Swaminathan ◽  
G. Lakshminarayanan ◽  
Seok-Bum Ko
Keyword(s):  
Low Power ◽  
High Speed ◽  
Network On Chip ◽  
Network Interface ◽  
Ping Pong ◽  
On Chip

INFLUENCE OF TRAFFIC CORRELATION ON THE PERFORMANCE OF NETWORK-ON-CHIP DESIGNS

2010 ◽  
Vol 19 (03) ◽  
pp. 655-669 ◽  
Author(s):  
FANG WANG
Keyword(s):  
High Speed ◽  
Communication Complexity ◽  
Network On Chip ◽  
Strong Correlations ◽  
Communication Performance ◽  
Seamless Integration ◽  
High Speed Network ◽  
On Chip ◽  
Point To Point ◽  
The Impact

Advance in semiconductor technologies enables seamless integration of hundreds of cores on a single silicon die, which requires high communication performance. To deal with the increasing communication complexity of System-on-Chip (SoC), Network-on-Chip (NoC) has been recently proposed as an alternative to the conventional point-to-point links and bus based communication fabrics. In practice, to facilitate NoC design evaluation and optimization, Poisson traffic or Bernoulli traffic models are generally assumed. However, actual measurements showed that real high speed network traffic always has strong correlations. The objective of this paper is to investigate the impact of traffic correlations on the performance of NoC design. Experimental results show that traffic correlation degrades the performance of NoC design and unrealistic traffic assumptions may yield unacceptable designs.

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