scholarly journals Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links

2017 ◽  
Author(s):  
Sebastian Werner ◽  
Javier Navaridas ◽  
Mikel Lujan
Keyword(s):  
Low Power ◽  
Low Latency ◽  
Networks On Chip ◽  
Optical Links ◽  
On Chip

scholarly journals Design of Efficient Router with Low Power and Low Latency for Network on Chip

2016 ◽  
Vol 07 (04) ◽  
pp. 339-349
Author(s):  
M. Deivakani ◽  
D. Shanthi
Keyword(s):  
Low Power ◽  
Network On Chip ◽  
Low Latency ◽  
On Chip

scholarly journals Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip

2015 ◽  
Vol 11 (3) ◽  
pp. 552-566 ◽  
Author(s):  
Maurizio Palesi ◽  
Davide Patti ◽  
Giuseppe Ascia ◽  
Daniela Panno ◽  
Vincenzo Catania
Keyword(s):  
Low Power ◽  
Routing Algorithm ◽  
Power Networks ◽  
Networks On Chip ◽  
Data Encoding ◽  
On Chip

scholarly journals A low latency and low power indirect topology for on-chip communication

PLoS ONE ◽  
2019 ◽  
Vol 14 (10) ◽  
pp. e0222759
Author(s):  
Usman Ali Gulzari ◽  
Sarzamin Khan ◽  
Muhammad Sajid ◽  
Sheraz Anjum ◽  
Frank Sill Torres ◽  
...  
Keyword(s):  
Low Power ◽  
Low Latency ◽  
On Chip
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