Multithreaded virtual-memory-enabled reconfigurable hardware accelerators

2006 ◽  
Author(s):  
Miljan Vuletic ◽  
Paolo Ienne ◽  
Christopher Claus ◽  
Walter Stechele
Keyword(s):  
Virtual Memory ◽  
Reconfigurable Hardware ◽  
Hardware Accelerators

scholarly journals On-Chip Reconfigurable Hardware Accelerators for Popcount Computations

2016 ◽  
Vol 2016 ◽  
pp. 1-11 ◽  
Author(s):  
Valery Sklyarov ◽  
Iouliia Skliarova ◽  
João Silva
Keyword(s):  
Processing System ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Hardware Accelerators ◽  
Programmable Logic ◽  
Combinatorial Search ◽  
Pci Express ◽  
Systems On Chip ◽  
Search Data ◽  
On Chip

Popcount computations are widely used in such areas as combinatorial search, data processing, statistical analysis, and bio- and chemical informatics. In many practical problems the size of initial data is very large and increase in throughput is important. The paper suggests two types of hardware accelerators that are (1) designed in FPGAs and (2) implemented in Zynq-7000 all programmable systems-on-chip with partitioning of algorithms that use popcounts between software of ARM Cortex-A9 processing system and advanced programmable logic. A three-level system architecture that includes a general-purpose computer, the problem-specific ARM, and reconfigurable hardware is then proposed. The results of experiments and comparisons with existing benchmarks demonstrate that although throughput of popcount computations is increased in FPGA-based designs interacting with general-purpose computers, communication overheads (in experiments with PCI express) are significant and actual advantages can be gained if not only popcount but also other types of relevant computations are implemented in hardware. The comparison of software/hardware designs for Zynq-7000 all programmable systems-on-chip with pure software implementations in the same Zynq-7000 devices demonstrates increase in performance by a factor ranging from 5 to 19 (taking into account all the involved communication overheads between the programmable logic and the processing systems).

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