scholarly journals On-Chip Reconfigurable Hardware Accelerators for Popcount Computations

2016 ◽  
Vol 2016 ◽  
pp. 1-11 ◽  
Author(s):  
Valery Sklyarov ◽  
Iouliia Skliarova ◽  
João Silva
Keyword(s):  
Processing System ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Hardware Accelerators ◽  
Programmable Logic ◽  
Combinatorial Search ◽  
Pci Express ◽  
Systems On Chip ◽  
Search Data ◽  
On Chip

Popcount computations are widely used in such areas as combinatorial search, data processing, statistical analysis, and bio- and chemical informatics. In many practical problems the size of initial data is very large and increase in throughput is important. The paper suggests two types of hardware accelerators that are (1) designed in FPGAs and (2) implemented in Zynq-7000 all programmable systems-on-chip with partitioning of algorithms that use popcounts between software of ARM Cortex-A9 processing system and advanced programmable logic. A three-level system architecture that includes a general-purpose computer, the problem-specific ARM, and reconfigurable hardware is then proposed. The results of experiments and comparisons with existing benchmarks demonstrate that although throughput of popcount computations is increased in FPGA-based designs interacting with general-purpose computers, communication overheads (in experiments with PCI express) are significant and actual advantages can be gained if not only popcount but also other types of relevant computations are implemented in hardware. The comparison of software/hardware designs for Zynq-7000 all programmable systems-on-chip with pure software implementations in the same Zynq-7000 devices demonstrates increase in performance by a factor ranging from 5 to 19 (taking into account all the involved communication overheads between the programmable logic and the processing systems).

scholarly journals Modeling and Simulation of Network-on-Chip Systems with DEVS and DEUS

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Michele Amoretti
Keyword(s):  
Modeling And Simulation ◽  
Discrete Event ◽  
General Purpose ◽  
System Specification ◽  
Modeling Framework ◽  
Steep Learning Curve ◽  
Networks On Chip ◽  
Systems On Chip ◽  
Communication Architectures ◽  
On Chip

Networks on-chip (NoCs) provide enhanced performance, scalability, modularity, and design productivity as compared with previous communication architectures for VLSI systems on-chip (SoCs), such as buses and dedicated signal wires. Since the NoC design space is very large and high dimensional, evaluation methodologies rely heavily on analytical modeling and simulation. Unfortunately, there is no standard modeling framework. In this paper we illustrate how to design and evaluate NoCs by integrating the Discrete Event System Specification (DEVS) modeling framework and the simulation environment called DEUS. The advantage of such an approach is that both DEVS and DEUS support modularity—the former being a sound and complete modeling framework and the latter being an open, general-purpose platform, characterized by a steep learning curve and the possibility to simulate any system at any level of detail.

scholarly journals Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing

Technologies ◽  
2020 ◽  
Vol 8 (1) ◽  
pp. 10
Author(s):  
Jan Moritz Joseph ◽  
Dominik Ermel ◽  
Lennart Bamberg ◽  
Alberto García-Oritz ◽  
Thilo Pionteck
Keyword(s):  
Simulated Annealing ◽  
Cost Function ◽  
Linear Models ◽  
Nonlinear Models ◽  
General Purpose ◽  
Network Graph ◽  
Systems On Chip ◽  
On Chip ◽  
Core Mapping ◽  
Application Specific

Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip. In conventional multiprocessors, this mapping is area-agnostic as the cores in the core graph are uniform and therefore iso-area. This changes for Systems-on-Chip because tasks are mapped to specific blocks and not general-purpose cores. Thus, the area of these specific cores is varying. This requires novel mapping methods. In this paper, we propose a an area-aware cost function for simulated annealing; Furthermore, we advocate the use of nonlinear models as the area is nonlinear: A semi-definite program (SDP) can be used as it is sufficiently fast and shows 20% better area than conventional linear models. Our cost function allows for up to 16.4% better area, 2% better communication (bandwidth times hop distance) and 13.8% better total bandwidth in the network in comparison to the standard approach that accounts for both the network communication and uses cores with varying areas as well.

scholarly journals Performance analysis of general purpose and digital signal processor kernels for heterogeneous systems-on-chip

2003 ◽  
Vol 1 ◽  
pp. 171-175
Author(s):  
T. von Sydow ◽  
H. Blume ◽  
T. G. Noll
Keyword(s):  
Digital Signal Processor ◽  
Design Space Exploration ◽  
Heterogeneous Systems ◽  
Digital Signal ◽  
General Purpose ◽  
Optimization Techniques ◽  
Product Cycle ◽  
Systems On Chip ◽  
Programmable Architecture ◽  
On Chip

Abstract. Various reasons like technology progress, flexibility demands, shortened product cycle time and shortened time to market have brought up the possibility and necessity to integrate different architecture blocks on one heterogeneous System-on-Chip (SoC). Architecture blocks like programmable processor cores (DSP- and GPP-kernels), embedded FPGAs as well as dedicated macros will be integral parts of such a SoC. Especially programmable architecture blocks and associated optimization techniques are discussed in this contribution. Design space exploration and thus the choice which architecture blocks should be integrated in a SoC is a challenging task. Crucial to this exploration is the evaluation of the application domain characteristics and the costs caused by individual architecture blocks integrated on a SoC. An ATE-cost function has been applied to examine the performance of the aforementioned programmable architecture blocks. Therefore, representative discrete devices have been analyzed. Furthermore, several architecture dependent optimization steps and their effects on the cost ratios are presented.

Adaptive multi-layer techniques for increased system dependability

2015 ◽  
Vol 57 (3) ◽  
Author(s):  
Lars Bauer ◽  
Jörg Henkel ◽  
Andreas Herkersdorf ◽  
Michael A. Kochte ◽  
Johannes M. Kühn ◽  
...  
Keyword(s):  
General Purpose ◽  
System Level ◽  
Coarse Grained ◽  
Common Goal ◽  
Fine Grained ◽  
Reconfigurable Processors ◽  
Systems On Chip ◽  
On Chip ◽  
Application Specific ◽  
Heterogeneous Mpsoc

AbstractAchieving system-level dependability is a demanding task. The manifold requirements and dependability threats can no longer be statically addressed at individual abstraction layers. Instead, all components of future multi-processor systems-on-chip (MPSoCs) have to contribute to this common goal in an adaptive manner.In this paper we target a generic heterogeneous MPSoC that combines general purpose processors along with dedicated application-specific hard-wired accelerators, fine-grained reconfigurable processors, and coarse-grained reconfigurable architectures. We present different

The Design of PLC SOC Controller by Dual-Core Mutually Exclusive Processor

2011 ◽  
Vol 383-390 ◽  
pp. 5663-5668
Author(s):  
Liang Liang Liu ◽  
Peng Long Jiang
Keyword(s):  
Mutual Exclusion ◽  
General Purpose ◽  
System On Chip ◽  
The Other ◽  
Data Consistency ◽  
Programmable Logic ◽  
Process Unit ◽  
General Purpose Processor ◽  
On Chip ◽  
Dual Core

The Programmable Logic Controller (PLC) market is mainly dominated by Omron, Schneider, NEC and other foreign manufacturers. The CPU module of their PLC products usually has two processors at PCB level. One of the processors is general-purpose processor and the other is Ladder Chart Hardware Process Unit (LPU). Based on the research of dual-core mutual exclusion, interrupt management and data consistency issues of the LEON2 of Gaisler Research, the LPU processor and LEON2 processor are integrated in a chip on mutually exclusive SOC (System On Chip) architecture. It is proved by simulation that the PLC SOC controller works steadily and efficiently.

Effective Memory Architectures of Multi-Processor Systems-on-Chip

2010 ◽  
Vol 3 (3) ◽  
pp. 218-231
Author(s):  
Ni Zhou ◽  
Fei Qiao ◽  
Huazhong Yang ◽  
Hui Wang
Keyword(s):  
Systems On Chip ◽  
On Chip ◽  
Memory Architectures
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