International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)
Latest Publications

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Published By IEEE

0769525547

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06) ◽

10.1109/parelec.2006.4 ◽

2006 ◽

Author(s):

B. Fechner

Keyword(s):

Fault Tolerant

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Parallel Linear Hashtable Motion Estimation Algorithm for Parallel Video Processing

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06) ◽

10.1109/parelec.2006.60 ◽

2006 ◽

Author(s):

Yunsong Wu ◽

G. Megson

Keyword(s):

Motion Estimation ◽

Video Processing ◽

Estimation Algorithm ◽

Parallel Video Processing ◽

Motion Estimation Algorithm

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A Fast Parallel Dynasearch Algorithm for Some Scheduling Problems

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06) ◽

10.1109/parelec.2006.3 ◽

2006 ◽

Cited By ~ 2

Author(s):

W. Bozejko ◽

M. Wodecki

Keyword(s):

Scheduling Problems

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Performance Evaluation of Different Kohenen Network Parallelization Techniques

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06) ◽

10.1109/parelec.2006.66 ◽

2006 ◽

Cited By ~ 2

Author(s):

J. Kwiatkowski ◽

M. Pawlik ◽

U. Markowska-Kaczmar ◽

D. Konieczny

Keyword(s):

Performance Evaluation

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Scalable and Parallel Aggregated Bit Vector Packet Classification Using Prefix Computation Model

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06) ◽

10.1109/parelec.2006.71 ◽

2006 ◽

Cited By ~ 3

Author(s):

T. Srinivasan ◽

N. Dhanasekar ◽

M. Nivedita ◽

R. Dhivyakrishnan ◽

A.A. Azeezunnisa

Keyword(s):

Packet Classification ◽

Computation Model ◽

Bit Vector

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Complexity of Collective Communications on NoCs

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06) ◽

10.1109/parelec.2006.25 ◽

2006 ◽

Cited By ~ 5

Author(s):

J. Jaros ◽

M. Ohlidal ◽

V. Dvorak

Keyword(s):

Collective Communications

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Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06) ◽

10.1109/parelec.2006.62 ◽

2006 ◽

Cited By ~ 3

Author(s):

G. Pastuszak

Keyword(s):

Arithmetic Coding

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A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06) ◽

10.1109/parelec.2006.2 ◽

2006 ◽

Cited By ~ 1

Author(s):

A. Itradat ◽

M.O. Ahmad ◽

A. Shatnawi

Keyword(s):

Static Scheduling ◽

Multiprocessor Architectures ◽

Dsp Applications

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Enabling Reconfigurable Hardware Accelerators for the Grid

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06) ◽

10.1109/parelec.2006.34 ◽

2006 ◽

Author(s):

S. Dydel ◽

K. Benedyczak ◽

P. Bala

Keyword(s):

Reconfigurable Hardware ◽

Hardware Accelerators

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Automatic High Voltage Apparatus Optimization: Making it More Engineer-Friendly

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06) ◽

10.1109/parelec.2006.19 ◽

2006 ◽

Cited By ~ 1

Author(s):

C. Trinitis

Keyword(s):

High Voltage

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International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments

Parallel Linear Hashtable Motion Estimation Algorithm for Parallel Video Processing

A Fast Parallel Dynasearch Algorithm for Some Scheduling Problems

Performance Evaluation of Different Kohenen Network Parallelization Techniques

Scalable and Parallel Aggregated Bit Vector Packet Classification Using Prefix Computation Model

Complexity of Collective Communications on NoCs

Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding

A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures

Enabling Reconfigurable Hardware Accelerators for the Grid

Automatic High Voltage Apparatus Optimization: Making it More Engineer-Friendly

International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)
Latest Publications