High Threshold Voltage Matching Performance on Gate-All-Around MOSFET

2006 ◽  
Author(s):  
Augustin Cathignol ◽  
Antoine Cros ◽  
Samuel Harrison ◽  
Robin Cerrutti ◽  
Philippe Coronel ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
High Threshold ◽  
Matching Performance

High threshold voltage matching performance on gate-all-around MOSFET

2007 ◽  
Vol 51 (11-12) ◽  
pp. 1450-1457 ◽  
Author(s):  
Augustin Cathignol ◽  
Antoine Cros ◽  
Samuel Harrison ◽  
Robin Cerrutti ◽  
Philippe Coronel ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
High Threshold ◽  
Matching Performance

1200 V SiC IE-UMOSFET with Low On-Resistance and High Threshold Voltage

2017 ◽  
Vol 897 ◽  
pp. 497-500 ◽  
Author(s):  
Shinsuke Harada ◽  
Yusuke Kobayashi ◽  
A. Kinoshita ◽  
N. Ohse ◽  
Takahito Kojima ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Voltage ◽  
Gate Oxide ◽  
Critical Issue ◽  
High Threshold ◽  
Trade Off ◽  
Negative Gate Voltage

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.

Normally-off operation AlGaN/GaN MOS-HEMT with high threshold voltage

2010 ◽  
Vol 46 (18) ◽  
pp. 1280 ◽  
Author(s):  
C.-T. Chang ◽  
T.-H. Hsu ◽  
E.Y. Chang ◽  
Y.-C. Chen ◽  
H.-D. Trinh ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
High Threshold

Effect of High Temperature Forming Gas Annealing on Electrical Properties of 4H-SiC Lateral MOSFETs with Lanthanum Silicate and ALD SiO2 Gate Dielectric

2018 ◽  
Vol 924 ◽  
pp. 482-485
Author(s):  
Min Seok Kang ◽  
Kevin Lawless ◽  
Bong Mook Lee ◽  
Veena Misra
Keyword(s):  
Threshold Voltage ◽  
Interfacial Layer ◽  
Field Effect ◽  
Lanthanum Oxide ◽  
Gate Dielectric ◽  
High Mobility ◽  
High Threshold ◽  
Field Effect Mobility ◽  
The Impact ◽  
Lanthanum Silicate

We investigated the impact of an initial lanthanum oxide (La2O3) thickness and forming gas annealing (FGA) conditions on the MOSFET performance. The FGA has been shown to dramatically improve the threshold voltage (VT) stability of 4H-SiC MOSFETs. The FGA process leads to low VTshift and high field effect mobility due to reduction of the interface states density as well as traps by passivating the dangling bonds and active traps in the Lanthanum Silicate dielectrics. By optimizing the La2O3interfacial layer thickness and FGA condition, SiC MOSFETs with high threshold voltage and high mobility while maintaining minimal VTshift are realized.

scholarly journals Different electrode anodes used in OLED devices Diferentes eletrodos anodos usados em dispositivos OLEDs

2021 ◽  
Author(s):  
Emerson Roberto Santos ◽  
Thiago de Carvalho Fullenbach ◽  
Marina Sparvoli Medeiros ◽  
Luis da Silva Zambom ◽  
Roberto Koji Onmori ◽  
...  
Keyword(s):  
Thin Films ◽  
Tin Oxide ◽  
Threshold Voltage ◽  
Indium Tin Oxide ◽  
Light Emitting Diode ◽  
Electrical Current ◽  
High Threshold ◽  
Diamond Coatings ◽  
Ito Thin Films ◽  
Order Of Magnitude

Transparent conductive oxides (TCOs) known as indium tin oxide (ITO) and fluorine tin oxide (FTO) deposited on glass were compared by different techniques and also as anodes in organic light-emitting diode (OLED) devices with same structure. ITO produced at laboratory was compared with the commercial one manufactured by different companies: Diamond Coatings, Displaytech and Sigma-Aldrich, and FTO produced at laboratory was compared with the commercial one manufactured by Flexitec Company. FTO thin films produced at laboratory presented the lowest performance measured by Hall effect technique and also by I-V curve of OLED device with low electrical current and high threshold voltage. ITO thin films produced at laboratory presented elevated sheet resistance in comparison with commercial ITOs (approximately one order of magnitude greater), that can be related by a high number of defects as discontinuity of the chemical lattice or low crystalline structure. In the assembly of OLED devices with ITO and FTO produced at laboratory, neither presented luminances. ITO manufactured by Sigma-Aldrich company presented better electrical and optical characteristics, as low electrical resistivity, good wettability, favorable transmittance, perfect physicalchemical stability and lowest threshold voltage (from 3 to 4.5 V) for OLED devices.

scholarly journals High Threshold Voltage Normally off Ultra-Thin-Barrier GaN MISHEMT with MOCVD-Regrown Ohmics and Si-Rich LPCVD-SiNx Gate Insulator

Energies ◽  
2020 ◽  
Vol 13 (10) ◽  
pp. 2479
Author(s):  
Hsiang-Chun Wang ◽  
Hsien-Chin Chiu ◽  
Chong-Rong Huang ◽  
Hsuan-Ling Kao ◽  
Feng-Tso Chien
Keyword(s):  
Threshold Voltage ◽  
Gate Insulator ◽  
High Threshold ◽  
Potential Candidate ◽  
Channel Mobility ◽  
Switching Power ◽  
Selective Area ◽  
Inversion Channel ◽  
Threshold Voltage Distribution ◽  
Dimensional Electron Gas

A high threshold voltage (VTH) normally off GaN MISHEMTs with a uniform threshold voltage distribution (VTH = 4.25 ± 0.1 V at IDS = 1 μA/mm) were demonstrated by the selective area ohmic regrowth technique together with an Si-rich LPCVD-SiNx gate insulator. In the conventional GaN MOSFET structure, the carriers were induced by the inversion channel at a high positive gate voltage. However, this design sacrifices the channel mobility and reliability because a huge number of carriers are beneath the gate insulator directly during operation. In this study, a 3-nm ultra-thin Al0.25Ga0.75N barrier was adopted to provide a two-dimensional electron gas (2DEG) channel underneath the gate terminal and selective area MOCVD-regrowth layer to improve the ohmic contact resistivity. An Si-rich LPCVD-SiNx gate insulator was employed to absorb trace oxygen contamination on the GaN surface and to improve the insulator/GaN interface quality. Based on the breakdown voltage, current density, and dynamic RON measured results, the proposed LPCVD-MISHEMT provides a potential candidate solution for switching power electronics.

Recessed-gate enhancement-mode GaN HEMT with high threshold voltage

2005 ◽  
Vol 41 (7) ◽  
pp. 449 ◽  
Author(s):  
W.B. Lanford ◽  
T. Tanaka ◽  
Y. Otoki ◽  
I. Adesida
Keyword(s):  
Threshold Voltage ◽  
High Threshold ◽  
Enhancement Mode ◽  
Gan Hemt ◽  
Recessed Gate

Electrical and microstructural characteristics of ZnO–Bi2O3-based varistors doped with rare-earth oxides

2001 ◽  
Vol 16 (10) ◽  
pp. 2817-2823 ◽  
Author(s):  
Nguyen The Hung ◽  
Nguyen Dinh Quang ◽  
Slavko Bernik
Keyword(s):  
Rare Earth ◽  
Energy Absorption ◽  
Threshold Voltage ◽  
Spinel Phase ◽  
High Energy ◽  
Absorption Capacity ◽  
Rare Earth Oxides ◽  
High Threshold ◽  
Energy Absorption Capacity ◽  
High Energy Absorption

ZnO-based varistor samples with a relatively high Sb2O3 to Bi2O3 ratio of 5 were fired at 1200 °C and found to have a high threshold voltage (VT) of 280 V/mm and a low energy-absorption capacity of 50 J/cm3. The introduction of rare-earth oxides (REO) increased the energy-absorption capacity of Pr6O11- and Nd2O3-doped samples to 110 J/cm3 while their threshold voltage (VT) remained slightly above 300 V/mm. Doping with Pr6O11 and Nd2O3 altered the formation of the spinel phase and significantly changed its particle size and distribution which, as a result, had a positive effect on the energy-absorption capacity of the REO-doped samples. Doping with small amounts of Pr6O11 and Nd2O3 appears to be promising for the preparation of ZnO-based varistors with a high breakdown voltage and a high energy absorption capacity.

scholarly journals A Novel Design of Low-Power 1-Bit CMOS Full-Adder Cell using XNOR and MUX

2013 ◽  
Vol 7 (3) ◽  
pp. 1155-1165
Author(s):  
Dayadi Lakshmaiah ◽  
Dr. M.V. Subramanyam ◽  
Dr. K.Sathya Prasad
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Supply Voltage ◽  
Full Adder ◽  
High Threshold ◽  
Low Threshold ◽  
Supply Voltage Scaling ◽  
Critical Paths ◽  
Power Delay Product ◽  
Novel Design

This paper process a novel design for low power 1-bit CMOS full adder using XNOR and MUX, with reduced number of transistors using GDI cell. The circuits were simulated with supply voltage scaling from 1.2V to 0.6V &0.6V to 0.3V. To achieve the desired performance of power delay product, area, capacitance the transistors with low threshold voltage were used at critical paths and high threshold voltage at non critical paths. The results show the efficiency of the proposed technique in terms of power consumption, delay and area.

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