A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs

2011 ◽  
Author(s):  
Yuji Osaki ◽  
Tetsuya Hirose ◽  
Nobutaka Kuroki ◽  
Masahiro Numa
Keyword(s):  
Error Correction ◽  
Low Voltage ◽  
Digital Cmos ◽  
Level Shifter

A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs

2012 ◽  
Vol 47 (7) ◽  
pp. 1776-1783 ◽  
Author(s):  
Yuji Osaki ◽  
Tetsuya Hirose ◽  
Nobutaka Kuroki ◽  
Masahiro Numa
Keyword(s):  
Low Power ◽  
Error Correction ◽  
Low Voltage ◽  
Power Level ◽  
Digital Cmos ◽  
Level Shifter

A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs

2015 ◽  
Author(s):  
Ryo Matsuzuka ◽  
Tetsuya Hirose ◽  
Yuzuru Shizuku ◽  
Nobutaka Kuroki ◽  
Masahiro Numa
Keyword(s):  
Energy Level ◽  
Low Voltage ◽  
Low Energy ◽  
Level Shifter

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

2013 ◽  
Vol 373-375 ◽  
pp. 1607-1611
Author(s):  
Hong Gang Zhou ◽  
Shou Biao Tan ◽  
Qiang Song ◽  
Chun Yu Peng
Keyword(s):  
Error Correction ◽  
Low Voltage ◽  
Cmos Technology ◽  
Soft Error ◽  
Error Correction Codes ◽  
Cell Design ◽  
Low Voltage Operation ◽  
Sram Cell ◽  
Simulation Results ◽  
Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

scholarly journals An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI

2019 ◽  
Vol 66 (6) ◽  
pp. 899-903
Author(s):  
Ali Asghar Vatanjou ◽  
Trond Ytterdal ◽  
Snorre Aunet
Keyword(s):  
Energy Level ◽  
Low Voltage ◽  
Low Energy ◽  
Level Shifter ◽  
28 Nm

scholarly journals An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs

2017 ◽  
Vol 64 (8) ◽  
pp. 2026-2035 ◽  
Author(s):  
Ryo Matsuzuka ◽  
Tetsuya Hirose ◽  
Yuzuru Shizuku ◽  
Kyohei Shinonaga ◽  
Nobutaka Kuroki ◽  
...  
Keyword(s):  
Energy Level ◽  
Low Voltage ◽  
Low Energy ◽  
Level Shifter ◽  
Conversion Range
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