Board level flat and vertical drop impact reliability for wafer level chip scale package

2011 ◽  
Author(s):  
Richard Qian ◽  
Yong Liu ◽  
Jihwan Kim ◽  
Stephen Martin
Keyword(s):  
Drop Impact ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Impact Reliability ◽  
Board Level

Low Profile and Large Size WLCSP in IoT Applications

2019 ◽  
Vol 2019 (1) ◽  
pp. 000327-000332
Author(s):  
Tom Tang ◽  
Kuei Hsiao Kuo ◽  
Victor Lin ◽  
Kelly Chen ◽  
J.Y. Chen ◽  
...  
Keyword(s):  
High Performance ◽  
Wafer Level ◽  
Joint Reliability ◽  
Large Size ◽  
Low Profile ◽  
Chip Scale Package ◽  
Iot Devices ◽  
Small Form Factor ◽  
Board Level ◽  
Board Level Reliability

Abstract Recently, Wafer Level Chip Scale Package (WLCSP) Package is being rapidly adopted in Internet of Things (IoT) and consumer mobile electronics due to its low profile, small form factor and relatively easy assembly process. WLCSP with large die size becomes the trend in fulfilling high performance product demands. However, the solder joint reliability performances of WLCSP is the key challenge and becomes critical as increasing die size, especially the size is larger than 6 × 6 mm2. There is also growing interest in low profile WLCSP packages to less than 300 microns, especially when they are placed in a limited space inside IoT devices. Thin wafers are fragile and must be supported over their full dimensions to prevent cracking and breakage. An increasingly popular approach to thin wafer handling involves grinding and taping thin wafers with in-line machines. A specific carry tape have been also developed for transferring thin wafers after thinning. In this paper, WLCSP board level reliability for both large die size and low profile was studied, a test vehicle used for the large WLCSP package testing has 350um ball pitch and fully populated array. In addition to board level reliability test simulation and data collection, processing challenges were discussed, as well as processing solutions for thin wafer handling.

Board Level Reliability Enhancement for A Double-bump Wafer Level Chip Scale Package

2004 ◽  
Vol 1 (2) ◽  
pp. 64-71 ◽  
Author(s):  
Xiaowu Zhang ◽  
E. H. Wong ◽  
Mahadevan K. Iyer
Keyword(s):  
Solder Joint ◽  
Design Guidelines ◽  
Wafer Level ◽  
Element Analysis ◽  
Chip Scale Package ◽  
Form Design ◽  
Parametric Studies ◽  
Reliability Enhancement ◽  
Board Level ◽  
Board Level Reliability

This paper presents a nonlinear finite element analysis on board level solder joint reliability enhancement of a double-bump wafer level chip scale package (CSP). A viscoplastic constitutive relation is adopted for the solders to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the modified Coffin-Manson equation, which has been verified by experimental results using one of the double-bump wafer level CSP packages as the test vehicle. A series of parametric studies were performed by changing the Sn/Ag inner bump size (UBM pad size and standoff height), the eutectic Sn/Pb external solder joint size (pad size and standoff height), pitch, die thickness, and the encapsulant thickness. The results obtained from the modeling are useful to form design guidelines for board level reliability enhancement of the wafer level CSP packages.

Board Level Drop Impact—Fundamental and Parametric Analysis

2005 ◽  
Vol 127 (4) ◽  
pp. 496-502 ◽  
Author(s):  
E. H. Wong ◽  
Y-W Mai ◽  
S. K. W. Seah
Keyword(s):  
Static Analysis ◽  
Bending Moment ◽  
Drop Impact ◽  
Computational Effort ◽  
Temperature Cycling ◽  
Mass System ◽  
Pcb Assembly ◽  
Impact Reliability ◽  
Board Level ◽  
Ic Package

A fundamental understanding of the dynamics of the PCB assembly when subjected to a half-sine acceleration has also been obtained through analyzing the PCB as a spring mass system, a beam, and a plate, respectively. The magnitude of stresses in solder interconnection due to flexing of the PCB is two orders higher than the magnitude of the stresses induced by acceleration and inertia loading the IC package. By ignoring the inertia loading, computational effort to evaluate the interconnection stresses due to PCB flexing can be reduced significantly via a two-step dynamic-static analysis. The dynamic analysis is first performed to evaluate the PCB bending moment adjacent the package, and is followed by a static analysis where the PCB bending moment is applied around the package. Parametric studies performed suggest a fundamental difference in designing for drop impact and designing for temperature cycling. The well-known design rules for temperature cycling—minimizing package length and maximizing interconnection standoff—does not work for drop impact. Instead, drop impact reliability can be enhanced by increasing the interconnection diameter, reducing the modulus of the interconnection materials, reducing the span of the PCB, or using either a very thin or a very thick PCB.

Board-Level Drop Impact Reliability of Silicon Interposer-Based 2.5-D IC Integration

2016 ◽  
Vol 6 (10) ◽  
pp. 1493-1504 ◽  
Author(s):  
Hsien-Chie Cheng ◽  
Tzu-Hsuan Cheng ◽  
Wen-Hwa Chen ◽  
Tao-Chih Chang ◽  
Hsin-Yi Huang
Keyword(s):  
Drop Impact ◽  
Impact Reliability ◽  
Board Level
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