3D-SoC integration utilizing high accuracy wafer level bonding

2016 ◽  
Author(s):  
Lan Peng ◽  
Soon-Wook Kim ◽  
Nancy Heylen ◽  
Maik Reichardt ◽  
Florian Kurz ◽  
...  
Keyword(s):  
High Accuracy ◽  
Wafer Level

(Invited) High Accuracy Aligned Wafer Bonding for Wafer-Level Integration

2018 ◽  
Vol 86 (5) ◽  
pp. 145-158 ◽  
Author(s):  
Thomas Plach ◽  
Bernhard Rebhan ◽  
Viorel Dragoi ◽  
Thomas Wagenleitner ◽  
Markus Wimplinger ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
High Accuracy ◽  
Wafer Level

High-quality multiple global layers on chip-redistributed wafer for wafer-level system integration using pseudo-SOC

2011 ◽  
Vol 2011 (1) ◽  
pp. 000820-000827
Author(s):  
Atsuko IIDA ◽  
Yutaka ONOZUKA ◽  
Hiroshi YAMADA ◽  
Toshihiko NAGANO ◽  
Kazuhiko ITAYA
Keyword(s):  
Low Temperature ◽  
System Integration ◽  
Fem Simulation ◽  
High Sensitivity ◽  
High Accuracy ◽  
System Level ◽  
Level System ◽  
Wafer Level ◽  
High Quality ◽  
On Chip

This paper reports an advanced process to realize high-quality multiple global layers on high-accuracy chip-redistributed wafer for wafer-level system integration using pseudo-SOC. We have been developing pseudo-SOC (p-SOC) technology by which KGD chips are integrated to a chip-redistributed wafer using high-rigidity epoxy resin and global layers with interconnecting chips are formed on it. The basic process has been established for p-SOC, and integration of MEMS and LSI, or front-end RF LSI and passive components, has been demonstrated. However, the first stage of p-SOC technology was based on a single global layer consisting of an insulating layer and a conductive layer, which limited the range of application. It is desirable to realize high-quality multiple global layers on the high-accuracy chip-redistributed wafer in order to expand its application toward system-level integration. For this purpose, it is necessary to keep all processes at low temperature for the reduction of warpage in the resin-based chip-redistributed wafer during several resin curing processes, to readjust resin-based materials, and to obtain high accuracy of chip position in chip-redistributed wafer. We developed the advanced p-SOC process to resolve these technical issues by improving the hardening process of resin, employing low-temperature-curing polyimide and optimizing the stress analysis by FEM simulation. As a result, realization of a novel one-chip module for a versatile high-sensitivity amplifier is demonstrated.

A New 1,000 kV Electron Microscope

1967 ◽  
Vol 25 ◽  
pp. 260-261
Author(s):  
M. Nishigaki ◽  
S. Katagiri ◽  
H. Kimura ◽  
B. Tadano
Keyword(s):  
Electron Microscope ◽  
High Voltage ◽  
Basic Research ◽  
Chromatic Aberration ◽  
High Accuracy ◽  
Biological Specimen ◽  
Voltage Electron ◽  
High Voltage Electron Microscope ◽  
High Voltage Electron

The high voltage electron microscope has many advantageous features in comparison with the ordinary electron microscope. They are a higher penetrating efficiency of the electron, low chromatic aberration, high accuracy of the selected area diffraction and so on. Thus, the high voltage electron microscope becomes an indispensable instrument for the metallurgical, polymer and biological specimen studies. The application of the instrument involves today not only basic research but routine survey in the various fields. Particularly for the latter purpose, the performance, maintenance and reliability of the microscope should be same as those of commercial ones. The authors completed a 500 kV electron microscope in 1964 and a 1,000 kV one in 1966 taking these points into consideration. The construction of our 1,000 kV electron microscope is described below.

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