Numerical study of preventing flow-induced die-shift in the compression molding for embedded wafer level packaging

2011 ◽  
Author(s):  
Lin Ji ◽  
Hyoung Joon Kim ◽  
FaXing Che ◽  
Shan Gao ◽  
Damaruganath Pinjala
Keyword(s):  
Numerical Study ◽  
Compression Molding ◽  
Wafer Level ◽  
Wafer Level Packaging

A numerical study on mitigation of flying dies in compression molding of microelectronic packages

2018 ◽  
Vol 2018 (1) ◽  
pp. 000355-000360
Author(s):  
Marc Dreissigacker ◽  
Ole Hoelck ◽  
Joerg Bauer ◽  
Tanja Braun ◽  
Karl-Friedrich Becker ◽  
...  
Keyword(s):  
Numerical Study ◽  
Compression Molding ◽  
Packaging Material ◽  
Process Conditions ◽  
Microelectronic Packaging ◽  
Wafer Level ◽  
Temperature Dependent ◽  
Wafer Level Packaging ◽  
Compression Speed ◽  
Complex Manner

Abstract Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds (EMC) depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dies during encapsulation in Fan-Out Wafer Level Packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemo-rheology, as well as to extract forces exerted on individual dies. It offers separate evaluation of pressure and shear-contributions for two cases, 0 ° and 45 ° between the dies' frontal area and the melt front. Process parameters, such as compression speed and process temperature, are determined to minimize flying dies and thereby maximize yield. The approach is easily scalable and is therefore well suited to face the challenges that come with the current efforts towards the transition from FOWLP to FOPLP (Fan-Out Panel Level Packaging).

scholarly journals A Numerical Study on Mitigation of Flying Dies in Compression Molding of Microelectronic Packages

2019 ◽  
Vol 16 (1) ◽  
pp. 39-44
Author(s):  
Marc Dreissigacker ◽  
Ole Hoelck ◽  
Joerg Bauer ◽  
Tanja Braun ◽  
Karl-Friedrich Becker ◽  
...  
Keyword(s):  
Process Parameters ◽  
Numerical Study ◽  
Compression Molding ◽  
Process Conditions ◽  
Wafer Level ◽  
Temperature Dependent ◽  
Drag Forces ◽  
Wafer Level Packaging ◽  
Arbitrary Geometries ◽  
Complex Manner

Abstract Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dice during encapsulation in fan-out wafer-level packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemorheology, and to extract forces exerted on individual dice. It offers separate evaluation of pressure and shear contributions for two cases, 0° and 45° between the dice' frontal area and the melt front. Process parameters, such as compression speed, thus cycle time, and process temperature, are determined to keep the forces on the dice below the critical level, where drag forces exceed adhesive forces. As a result, process parameters are determined to minimize flying dice and thereby maximize yield. The approach is easily transferable to arbitrary geometries and is therefore well suited to face the challenges that come with the current efforts toward the transition from FOWLP to larger substrates.

Development of compression molding process for Fan-Out wafer level packaging

2020 ◽  
Author(s):  
Bertheau Julien ◽  
Duval Fabrice F.C. ◽  
Kubota Tadashi ◽  
Bex Pieter ◽  
Kennes Koen ◽  
...  
Keyword(s):  
Compression Molding ◽  
Wafer Level ◽  
Molding Process ◽  
Wafer Level Packaging

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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