Comprehensive Investigation of Die Shift in Compression Molding Process for 12 Inch Fan-Out Wafer Level Packaging

2016 ◽  
Author(s):  
Yong Han ◽  
Mian Zhi Ding ◽  
Bu Lin ◽  
Chong Ser Choong
Keyword(s):  
Compression Molding ◽  
Wafer Level ◽  
Molding Process ◽  
Comprehensive Investigation ◽  
Wafer Level Packaging

Development of compression molding process for Fan-Out wafer level packaging

2020 ◽  
Author(s):  
Bertheau Julien ◽  
Duval Fabrice F.C. ◽  
Kubota Tadashi ◽  
Bex Pieter ◽  
Kennes Koen ◽  
...  
Keyword(s):  
Compression Molding ◽  
Wafer Level ◽  
Molding Process ◽  
Wafer Level Packaging

A numerical study on mitigation of flying dies in compression molding of microelectronic packages

2018 ◽  
Vol 2018 (1) ◽  
pp. 000355-000360
Author(s):  
Marc Dreissigacker ◽  
Ole Hoelck ◽  
Joerg Bauer ◽  
Tanja Braun ◽  
Karl-Friedrich Becker ◽  
...  
Keyword(s):  
Numerical Study ◽  
Compression Molding ◽  
Packaging Material ◽  
Process Conditions ◽  
Microelectronic Packaging ◽  
Wafer Level ◽  
Temperature Dependent ◽  
Wafer Level Packaging ◽  
Compression Speed ◽  
Complex Manner

Abstract Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds (EMC) depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dies during encapsulation in Fan-Out Wafer Level Packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemo-rheology, as well as to extract forces exerted on individual dies. It offers separate evaluation of pressure and shear-contributions for two cases, 0 ° and 45 ° between the dies' frontal area and the melt front. Process parameters, such as compression speed and process temperature, are determined to minimize flying dies and thereby maximize yield. The approach is easily scalable and is therefore well suited to face the challenges that come with the current efforts towards the transition from FOWLP to FOPLP (Fan-Out Panel Level Packaging).

Warpage Characterization of Molded Wafer for Fan-Out Wafer-Level Packaging

2019 ◽  
Vol 142 (1) ◽  
Author(s):  
Hsien-Chie Cheng ◽  
Yan-Cheng Liu
Keyword(s):  
Measurement Data ◽  
Mechanical Analysis ◽  
Volumetric Shrinkage ◽  
Heat Of Reaction ◽  
Wafer Level ◽  
Molding Process ◽  
Scanning Calorimetry ◽  
Molding Compound ◽  
Wafer Level Packaging

Abstract This study presents a comprehensive assessment of the process-induced warpage of molded wafer for chip-first, face-down fan-out wafer-level packaging (FOWLP) during the fan-out fabrication process. A process-dependent simulation methodology is introduced, which integrates nonlinear finite element (FE) analysis and element death-birth technique. The effects of the cure-dependent volumetric shrinkage, geometric nonlinearity, and gravity loading on the process-induced warpage are examined. The study starts from experimental characterization of the temperature-dependent material properties of the applied liquid type epoxy molding compound (EMC) system through dynamic mechanical analysis (DMA) and thermal mechanical analysis. Furthermore, its cure state (heat of reaction and degree of cure (DOC)) during the compression molding process (CMP) is measured by differential scanning calorimetry (DSC) tests. Besides, the cure dependent-volumetric (chemical) shrinkages of the EMC system after the in-mold cure (IMC) and postmold cure (PMC) are experimentally determined by which the volumetric shrinkage at the gelation point is predicted through a linear extrapolation approach. To demonstrate the effectiveness of the proposed theoretical model, the prediction results are compared against the inline warpage measurement data. One possible cause of the asymmetric/nonaxisymmetric warpage is also addressed. Finally, the influences of some geometric dimensions on the warpage of the molded wafer are identified through parametric analysis.

Advances in Temporary Bonding and Debonding Technologies for use with Wafer-Level System-in-Package (WLSiP) and Fan-Out Wafer-Level Packaging (FOWLP) Processes

2018 ◽  
Vol 2018 (1) ◽  
pp. 000051-000056 ◽  
Author(s):  
Michelle Fowler ◽  
John P. Massey ◽  
Matthew Koch ◽  
Kevin Edwards ◽  
Tanja Braun ◽  
...  
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
Active Area ◽  
Vertical Deformation ◽  
Level System ◽  
Wafer Level ◽  
Molding Process ◽  
Bonding Material ◽  
Wafer Level Packaging ◽  
Temporary Bonding ◽  
Mechanical Release

Abstract Today's complex fan-out wafer-level packaging (FOWLP) processes include the use of redistribution layers (RDL) and reconstituted wafers with epoxy mold compound (EMC) for use in heterogeneous integration [1]. Wafer-level system-in-package (WLSiP) uses fan-out wafer-level packaging (FOWLP) to build the system-in-package (SiP) by attaching know-good die (KGD) in a chip-first process to a tape laminated temporary carrier. If the dies are attached in a die-up configuration (active area facing up) and then over-molded with EMC, contact pads on the embedded die are exposed during the backside grind process. During the RDL build, the temporary carrier supplies mechanical support for the thinned substrate. In a die-down configuration with the active area facing down (eWLB), the temporary carrier is removed after the molding process thus exposing the contact pads for RDL build and solder ball mount. The ideal chip attachment scheme should minimize lateral movement of the die during over-mold (die shift) and also minimize vertical deformation of the bonding material. Thermal release tape provides a convenient way to attach die to a carrier prior to over-molding with EMC. However, not all bonding materials are suitable for presentation in tape form, so the material used in the tape may not be the optimal choice. An alternative method is to directly apply temporary bonding material to the carrier substrate. This enables the use of bonding materials with higher melt viscosity and improved thermal stability, resulting in less vertical deformation during die placement, and reduced die shift during over-molding. The bonding material will ideally have high adhesion to the EMC wafer to prevent delamination in the bond line during downstream processing. Stack stress and warpage is a major concern which causes handling and alignment problems during processing. The bonding material and carrier will need to be specifically suited to minimize the effects of stress in the compound wafer. Such material must balance rigidity with warp to prevent lateral die shift and deformation induced by coefficient of thermal expansion (CTE) mismatch between the carrier and EMC material [2]. Bonding materials must also have enough adhesion to the EMC material to overcome such stress without bond failure for an associated debond path (such as laser or mechanical release). In this experiment, we will examine a thermoplastic bonding material in combination with different release materials, addressing die shift, and deformation after EMC processing. Successful pairs will then undergo carrier release using either mechanical release or laser ablation release technology.

Investigation on Die Shift Issues in the 12-in Wafer-Level Compression Molding Process

2013 ◽  
Vol 3 (10) ◽  
pp. 1647-1653 ◽  
Author(s):  
Lin Bu ◽  
Siowling Ho ◽  
Sorono Dexter Velez ◽  
Taichong Chai ◽  
Xiaowu Zhang
Keyword(s):  
Compression Molding ◽  
Wafer Level ◽  
Molding Process

Mechanical Analyses of Advanced Multi-Chip Embedded Wafer Level Packages

2013 ◽  
Vol 740 ◽  
pp. 289-294
Author(s):  
Siow Ling Ho ◽  
Lin Bu ◽  
Dexter Velez Sorono ◽  
Ser Choong Chong ◽  
Tai Chong Chai ◽  
...  
Keyword(s):  
Cycling Performance ◽  
Market Demand ◽  
Wafer Level ◽  
Molding Process ◽  
Molding Compound ◽  
Mechanical Effects ◽  
Wafer Level Packaging ◽  
Attractive Option ◽  
Small Form Factor ◽  
Improved Accuracy

ncreasing functionality accompanied with device miniaturization in microelectronics has led to increased market demand for packages with small form factor. Over the years, embedded wafer level packaging (EWLP) has become an attractive option since it allows a reduction in package size and height. In the EWLP approach, the singulated dies are embedded within the molding compound through the wafer level compression molding process. For this study, critical mechanical challenges such as die shift and thermal cycling performance of a multi-chip embedded wafer level package (MCEWLP) are addressed through numerical modeling. For improved accuracy in die shift predictions, both mechanical effects and fluidic effects need to be taken into account. Mechanical effects account for around 75% of the die shift while fluidic effect contributes to the remaining 25%. It is shown that reducing the die size and the inclusion of UBM as a buffer layer can effectively increase the fatigue life of the packages.

Design and Optimization of Wafer-Level Compression Molding Process for One Chip Plus Multiple Decaps

2015 ◽  
Vol 5 (5) ◽  
pp. 606-613 ◽  
Author(s):  
Lin Bu ◽  
Siowling Ho ◽  
Sorono Dexter Velez ◽  
Lau Boon Long ◽  
Booyang Jung ◽  
...  
Keyword(s):  
Compression Molding ◽  
Wafer Level ◽  
Molding Process ◽  
Design And Optimization

Automated Optical Inspection (AOI) for FOPLP with Simultaneous Die Placement Metrology

2019 ◽  
Vol 2019 (1) ◽  
pp. 000203-000210
Author(s):  
Burhan Ali ◽  
Mike Marshall
Keyword(s):  
Process Control ◽  
Critical Dimension ◽  
Wafer Level ◽  
Molding Process ◽  
Packaging Process ◽  
Wafer Level Packaging ◽  
Optical Inspection ◽  
Pick And Place ◽  
Automated Optical Inspection ◽  
The Cost

Abstract As the final step of IC fabrication, packaging is the process to encapsulate the chip and provide the interconnections for the I/O of the final form factor. The demand for increasingly higher I/O density, shrinking device size and lower cost that drive wafer processing also apply to the packaging process. Various technologies have been developed in order to achieve these goals with most of them being wafer-level packaging (WLP). Unlike traditional packaging process, most I/O interconnections are done at the wafer-level with redistribution layers (RDLs). RDLs are the layer where copper lines and vias form the electrical connections. Depending on the applications' market such as mobile, memory or the Internet of Things (IoT), fan-out wafer level packaging (FOWLP) provides the most promising method to support the I/O density requirements and fine RDL line/space. Moreover, fan-out panel level packaging (FOPLP) was also developed in order to capitalize on economies of scale and optimize substrate utilization. In this technology, a rectangular substrate is used in the process instead of a round-shape substrate like a wafer. Processes and equipment have long been developed for the wafer substrate market, but the previous developments cannot be directly applied to panel substrates. For instance, in the wafer line, spin on processes are very prevalent but these are not at all practical for a panel line. Some capital equipment manufacturers have been reluctant to embrace panel-level manufacturing due to the uncertainty as to whether it will prevail. Struggles with yield have been very common; some of which are due to die placement and others due to the lack of process control capabilities. With the explosion and adoption of FOWLP to enhance package shrinkage and performance the panel market becomes more and more viable. The companies that have embraced panel level manufacturing from the beginning have a distinct advantage due to their intimate knowledge and experience with the substrates as well as the relationship developed with capital equipment suppliers to develop the necessary technology in order to process the panels. However, there is still a great need to ensure the product mix deployed in panel form can have an acceptable yield; automated optical inspection and die placement metrology bridge that gap. Automated optical inspection allows for defect detection with traditional bright field (BF) or dark field (DF) illumination and also a new novel illumination technique that enables the detection of organic particles and/or residues that are often used in panel-level packaging processes. A system capable of macro defect detection with sub-micron capabilities allows for multi-purpose panel inspections. The system is also equipped with metrology capabilities for critical dimension and die placement measurements which meet the process node dimensional requirements. These features allow for process control of pick and place, overlay as well as feed-forward capabilities for die placement corrections. In a FOWLP/FOPLP process, chip first and chip last can be concluded among all available methods in the market. Die placement either start from the initial phase of the process or in the final phase of the process. In the chip first scenario, the chips are placed on a carrier by a pick-and-place system and then followed by an encapsulating molding process to reconstitute a substrate (reconstituted wafer or reconstituted panel). At this point a semi-additive process (SAP) is typically followed which includes a photo resist layer being coated, exposed and developed following copper (Cu) plating in order to form the redistribution layer. In this workflow, the die position are dominated by the accuracy of the pick-and-place tool and coefficient of thermal expansion (CTE) mismatch of the molding material and carrier. The trade-off between throughputs, placement accuracy and a feedback mechanism is the main impact from the pick-and-place tool in this process step. This affects both the chip first and chip last scenarios. The thermal expansion of the molding process not only adds additional die shift but also causes warpage of the reconstituted substrate that becomes an issue for automated handling systems and local process variation. Therefore, to know the actual die position and orientation after the die placement and molding process is crucial for matching with the following redistribution layers development. In one scenario it is possible to utilize the lithography system to perform die position metrology, however, this is time consuming and impacts the cost of ownership and overall throughput for the lithography process. A solution to this problem is provided by implementation of an optical metrology system. Since this information needs to be passed to the lithography tool in a usable manner for variable exposure positioning, the alignment of the stage coordinate system between the die metrology tool and lithography tool is a key point to ensure the correctness of the feed forward loop. For RDL development overlay between die and RDL via directly impact yield and are just as critical to the process as defect inspection and critical dimension measurements. Based on the corrections for each die, a yield prediction can be made and provides different strategies for the lithography tool's exposure field in order to balance throughput and exposure yield rate. In this paper, we demonstrate a solution using an automatic optical inspection (AOI) system to perform the die metrology for chip placement and RDL development in FOPLP and FOWLP. This includes die shift, die rotation, RDL inspection as well as the overlap between a reconstituted substrate and RDLs. This solution provides comprehensive coverage for packaging process control and significantly impacts yield optimization and throughput enhancement. With a multifunctional AOI system, it also reduces the cost of ownership for packaging processes.

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