Strategies for Improving Reliability of Solder Joints on Power Semiconductor Devices

2003 ◽  
Author(s):  
Guo-Quan Lu ◽  
Xingsheng Liu ◽  
Sihua Wen ◽  
Jesus Noel Calata ◽  
John G. Bai
Keyword(s):  
Finite Element ◽  
Solder Joint ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Solder Joints ◽  
Mechanical Stresses ◽  
Flexible Substrates ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Reliability Of Solder Joints

There has been a significant research effort on area-array flip-chip solder joint technology in order to reduce package footprint, enhance current handling capability, and improve heat dissipation. However, there is a lingering concern over cyclic fatigue of solder alloys by thermo-mechanical stresses arising from mismatched thermal expansion coefficients of expansion among the various components of the package. In this paper, some strategies taken to improve the reliability of solder joints on power devices in single-device and multi-chip packages are presented. A strategy for improving solder joint reliability by adjusting solder joint geometry, underfilling and utilization of flexible substrates is discussed with emphasis on triple-stacked solder joints that resemble the shape of an hourglass. The hourglass shape relocates the highest inelastic strain away from the weaker interface with the chip to the bulk region of the joint while the underfill provides a load transfer from the joints. Flexible substrates can deform to relieve thermo-mechanical stresses. Thermal cycling data show significant improvements in reliability when these techniques are used. The design, testing, and finite-element analyses of an interconnection structure, termed the Dimple-Array Interconnect (DAI), for improving the solder joint reliability is also presented. In the DAI structure, a solder is used to join arrays of dimples pre-formed on a metal sheet onto the bonding pads of a device. Finite-element thermo-mechanical analyses and thermal cycling data show that the dimple-array solder joints are more fatigue-resistant than the conventional barrel-shaped solder joints in flip-chip IC packages.

Reliability Analysis of WLCSP Using Tie-Release Crack Prediction Finite Element Technique

2005 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Fatigue Life ◽  
Solder Joint ◽  
Solder Joints ◽  
Wafer Level ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Prediction Technique ◽  
Packaging Structure

For the purpose of enhancing the solder joint reliability of a wafer level chip scaling package (WLCSP), the WLCSP adopted the familiar design structure where both the stress compliant layer with low elastic modulus and the dummy solder joints are considered as structural supports. However, the predicted fatigue life of the solder joints at the internal part of the packaging structure using the conventional procedures of finite element simulation are higher than under actual conditions as a result of the perfect bonding assumption in the modeling. In this research, in order to improve the thermo-mechanical reliability of the solder joints, a node tie-release crack prediction technique, based on non-linear finite element analysis (FEA), is developed and compared with the estimation of the solder joint reliability using conventional methodology. The predicted results of reliability, using the novel prediction technique, show a lower fatigue life of the solder joint than that when using conventional one when the fracture regions in the dummy solder joints are simulated under quasi-steady state. At the same time, the result of the thermal cycling test also shows good agreement with the simulated result when using the proposed node tie-release crack prediction analysis.

Experimental evaluation of SnAgCu solder joint reliability in 100-μm pitch flip-chip assemblies

2014 ◽  
Vol 54 (5) ◽  
pp. 939-944 ◽  
Author(s):  
Ye Tian ◽  
Xi Liu ◽  
Justin Chow ◽  
Yi Ping Wu ◽  
Suresh K. Sitaraman
Keyword(s):  
Solder Joint ◽  
Experimental Evaluation ◽  
Flip Chip ◽  
Solder Joint Reliability ◽  
Snagcu Solder ◽  
Joint Reliability

Evaluation of solder joint reliability in flip chip package under thermal shock test

2006 ◽  
Vol 504 (1-2) ◽  
pp. 426-430 ◽  
Author(s):  
Dae-Gon Kim ◽  
Jong-Woong Kim ◽  
Seung-Boo Jung
Keyword(s):  
Solder Joint ◽  
Thermal Shock ◽  
Flip Chip ◽  
Thermal Shock Test ◽  
Solder Joint Reliability ◽  
Shock Test ◽  
Joint Reliability
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