A Single-Chip 5GHz WLAN Transmitter in 0.35μm Si/SiGe BiCMOS Technology

Author(s):  
F. Alimenti ◽  
M. Borgarino ◽  
R. Codeluppi ◽  
V. Palazzari ◽  
M. Pifferi ◽  
...  
Symmetry ◽  
2019 ◽  
Vol 11 (12) ◽  
pp. 1453 ◽  
Author(s):  
Andrey A. Kokolov ◽  
Dmitry A. Konkin ◽  
Artyom S. Koryakovtsev ◽  
Feodor I. Sheyerman ◽  
Leonid I. Babak

The design, simulation and experimental results of the integrated optical and electronic components for 25 Gb/s microwave photonic link based on a 0.25 µm SiGe:C BiCMOS technology process are presented. A symmetrical depletion-type Mach-Zehnder modulator (MZM) and driver amplifier are intended for electro-optical (E/O) integrated transmitters. The optical divider and combiner of MZM are designed based on the self-imaging theory and then simulated with EM software. In order to verify the correctness of the theory and material properties used in the simulation, a short test (prototype) MZM of 1.9 mm length is produced and measured. It shows an extinction ratio of 19 dB and half-wave voltage-length product of Vπ ∙ L = ~1.5 V·cm. Based on these results, the construction of the segmented modulator with several driver amplifier units is defined. The designed driver amplifier unit provides a bandwidth of more than 30 GHz, saturated output power of 6 dBm (output voltage of Vpp = 1.26 V), and matching better than −15 dB up to 35 GHz; it dissipates 170 mW of power and occupies an area of 0.4 × 0.38 mm2. The optical-electrical (O/E) receiver consists of a Ge-photodiode, transimpedance amplifier (TIA), and passive optical structures that are integrated on a single chip. The measured O/E 3 dB analog bandwidth of the integrated receiver is 22 GHz, and output matching is better than −15 dB up to 30 GHz, which makes the receiver suitable for 25 Gb/s links with intensity modulation. The receiver operates at 1.55 μm wavelength, uses 2.5 V and 3.3 V power supplies, dissipates 160 mW of power, and occupies an area of 1.46 × 0.85 mm2.


2015 ◽  
Vol 7 (3-4) ◽  
pp. 407-414 ◽  
Author(s):  
Mekdes G. Girma ◽  
Markus Gonser ◽  
Andreas Frischen ◽  
Jürgen Hasch ◽  
Yaoming Sun ◽  
...  

This paper describes the design considerations, integration issues, packaging, and experimental performance of recently developed D-Band dual-channel transceiver with on-chip antennas fabricated in a SiGe-BiCMOS technology. The design comprises a fully integrated transceiver circuit with quasi-monostatic architecture that operates between 114 and 124 GHz. All analog building blocks are controllable via a serial peripheral interface to reduce the number of connections and facilitate the communication between digital processor and analog building blocks. The two electromagnetically coupled patch antennas are placed on the top of the die with 8.6 dBi gain and have a simulated efficiency of 60%. The chip consumes 450 mW and is wire-bonded into an open-lid 5 × 5 mm2quad-flat no-leads package. Measurement results for the estimation of range, and azimuth angle in single object situation are presented.


2021 ◽  
Vol 68 (4) ◽  
pp. 1439-1445
Author(s):  
Hanbin Ying ◽  
Jeffrey W. Teng ◽  
John D. Cressler

2016 ◽  
Vol 64 (11) ◽  
pp. 3667-3677 ◽  
Author(s):  
Chao Liu ◽  
Qiang Li ◽  
Yihu Li ◽  
Xiao-Dong Deng ◽  
Hailin Tang ◽  
...  

Author(s):  
Nelson E. Lourenco ◽  
Robert L. Schmid ◽  
Kurt A. Moen ◽  
Stanley D. Phillips ◽  
Troy D. England ◽  
...  

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