Assessment of CMP Fill Pattern Effect on the Thermal Performance of Interconnects in Integrated Circuits BEOL

Accurate measurement of the thermal performance of vertically-stacked three-dimensional integrated circuits (3D ICs) is critical for optimal design and performance. Experimental measurements also help validate thermal models for predicting the temperature field in a 3D IC. This paper presents results from thermal measurements on a two-die 3D IC. The experimental setup and procedure is described. Transient and steady-state measurements are made while heating the top die or the bottom die. Results indicate that passage of electrical current through the heaters in top/bottom die induces a measureable temperature rise. There appears to be a unique asymmetry in thermal performance between the top die and the bottom die. The top die is found to heat up faster and more than the bottom die. Results presented in this paper are expected to play a key role in validation of simulation-based and analytical thermal models for 3D ICs, and lead to a better fundamental understanding of heat transport in stacked systems. This is expected to lead to effective thermal design and characterization tools for 3D ICs.

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Performance of Thermal Enhancements in Chip on Flex

10.1115/imece1999-0923 ◽

1999 ◽

Author(s):

Gary Miller ◽

Chittaranjan Sahay

Keyword(s):

Integrated Circuits ◽

Thermal Performance ◽

Building Blocks ◽

High Density ◽

Successful Implementation ◽

Engine Control ◽

General Electric ◽

Application Specific Integrated Circuits ◽

Thermal Enhancement ◽

Application Specific

Abstract The paper describes the development of encapsulated multiple chip on flex (COF) as Industry Common Building Blocks (CBB) as an economic alternative to high cost Application Specific Integrated Circuits (ASIC). Lockheed Martin/ General Electric developed the high density interconnect (HDI) structure used in these modules. The successful implementation of such CBB has been demonstrated in a F414 FADEC (Full Authority Digital Engine Control). The paper describes the construction of these COF CBB modules and their thermal performance with several thermal enhancement techniques.

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Some applications of electron beam microanalysis techniques in VLSI process evaluation

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s042482010007463x ◽

1983 ◽

Vol 41 ◽

pp. 160-161

Author(s):

Simon Thomas

Keyword(s):

Integrated Circuits ◽

Process Evaluation ◽

Large Scale ◽

Technology Development ◽

Analytical Techniques ◽

Successful Implementation ◽

Analysis Of Failures ◽

Characterization Of Materials ◽

Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

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The study of interfacial reactions of nickel thin films on GaAs

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100074616 ◽

1983 ◽

Vol 41 ◽

pp. 156-157

Author(s):

L.J. Chen ◽

Y.F. Hsieh

Keyword(s):

Thin Films ◽

Integrated Circuits ◽

Interfacial Reactions ◽

Metal Contacts ◽

Nickel Thin Films ◽

Thin Foils ◽

The Status ◽

Si Doped ◽

Electron Microscopes

One measure of the maturity of a device technology is the ease and reliability of applying contact metallurgy. Compared to metal contact of silicon, the status of GaAs metallization is still at its primitive stage. With the advent of GaAs MESFET and integrated circuits, very stringent requirements were placed on their metal contacts. During the past few years, extensive researches have been conducted in the area of Au-Ge-Ni in order to lower contact resistances and improve uniformity. In this paper, we report the results of TEM study of interfacial reactions between Ni and GaAs as part of the attempt to understand the role of nickel in Au-Ge-Ni contact of GaAs.N-type, Si-doped, (001) oriented GaAs wafers, 15 mil in thickness, were grown by gradient-freeze method. Nickel thin films, 300Å in thickness, were e-gun deposited on GaAs wafers. The samples were then annealed in dry N2 in a 3-zone diffusion furnace at temperatures 200°C - 600°C for 5-180 minutes. Thin foils for TEM examinations were prepared by chemical polishing from the GaA.s side. TEM investigations were performed with JE0L- 100B and JE0L-200CX electron microscopes.

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Microfabrication research at the National Submicron Facility

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100074331 ◽

1983 ◽

Vol 41 ◽

pp. 86-89

Author(s):

E.D. Wolf

Keyword(s):

Integrated Circuits ◽

Particle Physics ◽

High Speed ◽

New Technology ◽

High Energy ◽

High Energy Particle ◽

New Science ◽

Wide Range ◽

Intermediate Domain ◽

Circuit Function

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.

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Failure Analysis With the Scanning Electron Microscope

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100095662 ◽

1972 ◽

Vol 30 ◽

pp. 482-483

Author(s):

John R. Devaney

Keyword(s):

Electron Microscope ◽

Scanning Electron Microscope ◽

Integrated Circuits ◽

Failure Analysis ◽

High Reliability ◽

Military Applications ◽

Small Structure ◽

Useful Life ◽

Insight Into ◽

Scanning Electron

Occasionally in history, an event may occur which has a profound influence on a technology. Such an event occurred when the scanning electron microscope became commercially available to industry in the mid 60's. Semiconductors were being increasingly used in high-reliability space and military applications both because of their small volume but, also, because of their inherent reliability. However, they did fail, both early in life and sometimes in middle or old age. Why they failed and how to prevent failure or prolong “useful life” was a worry which resulted in a blossoming of sophisticated failure analysis laboratories across the country. By 1966, the ability to build small structure integrated circuits was forging well ahead of techniques available to dissect and analyze these same failures. The arrival of the scanning electron microscope gave these analysts a new insight into failure mechanisms.

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