A MEMS-Based Compliant Interconnect for Ultra-Fine-Pitch Wafer Level Packaging

2006 ◽  
Author(s):  
E.B. Liao ◽  
A.A.O. Tay ◽  
S.S.T. Ang ◽  
H.H. Feng ◽  
R. Nagarajan ◽  
...  
Keyword(s):  
Wafer Level ◽  
Wafer Level Packaging ◽  
Fine Pitch ◽  
Compliant Interconnect

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Failure Analysis ◽  
Dielectric Material ◽  
Organic Substrate ◽  
Wafer Level ◽  
Free Standing ◽  
Fine Pitch ◽  
Cross Section Area ◽  
Interconnect Reliability ◽  
Compliant Interconnect ◽  
Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

Fine Pitch(40μm) Integration Platform for Flexible Hybrid Electronics using Fan-Out Wafer-level Packaging

2018 ◽  
Vol 2018 (1) ◽  
pp. 000064-000068
Author(s):  
Amir Hanna ◽  
Arsalan Alam ◽  
G. Ezhilarasu ◽  
Subramanian S. Iyer
Keyword(s):  
High Performance ◽  
Metal Films ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Integration Platform ◽  
Wafer Level Packaging ◽  
Fine Pitch ◽  
Mechanical Bending

Abstract A flexible fan-out wafer-level packaging (FOWLP) process for heterogeneous integration of high performance dies in a flexible and biocompatible elastomeric package (FlexTrateTM) was used to assemble 625 dies with co-planarity and tilt <1μm, average die-shift of 3.28 μm with σ < 2.23 μm. Fine pitch interconnects (40μm pitch) were defined using a novel corrugated topography to mitigate the buckling phenomenon of metal films deposited on elastomeric substrates. Corrugated interconnects were then used to interconnect 200 dies, and then tested for cyclic mechanical bending reliability and have shown less than 7% change in resistance after bending down to 1 mm radius for 1,000 cycles.

Fine-Pitch RDL Integration for Fan-Out Wafer-Level Packaging

2020 ◽  
Author(s):  
Prayudi Lianto ◽  
Chin Wei Tan ◽  
Qi Jie Peng ◽  
Abdul Hakim Jumat ◽  
Xundong Dai ◽  
...  
Keyword(s):  
Wafer Level ◽  
Wafer Level Packaging ◽  
Fine Pitch

Ultra Fine Pitch RDL Development in Multi-layer eWLB (embedded Wafer Level BGA) Packages

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000809-000825
Author(s):  
Bernard Adams ◽  
Won Kyung Choi ◽  
Duk Ju Na ◽  
Andy Yong ◽  
Seung Wook Yoon ◽  
...  
Keyword(s):  
Line Width ◽  
High Performance ◽  
Process Development ◽  
Data Access ◽  
Electrical Performance ◽  
Logic Device ◽  
Wafer Level ◽  
Component Level ◽  
Wafer Level Packaging ◽  
Fine Pitch

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as eWLB (embedded Wafer Level Ball Grid Array), 2.5D interposers, thin PoP (Package-on-Package) and TSV (Through Silicon Via) interposer solutions to meet these needs. eWLB technologies with the ability to extend the package size beyond the area of the chip are leading the way to the next level of high density, thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low profile, low warpage 2.5D and 3D solutions. The use of these embedded eWLB packages in a side-by-side configuration to replace a stacked package configuration is critical to enable a more cost effective mobile market capability. Combining the analog or memory device with digital logic device in a semiconductor package can provide an optimum solution for achieving the best performance in thin, multiple-die integration aimed at very high performance. One of the greatest challenges facing wafer level packaging at present is the availability of routing and interconnecting high I/O fine pitch area array. RDL (redistribution layer) allows signal and supply I/O's to be redistributed to a footprint larger than the chip footprint in eWLB . Required line widths and spacing of 2/2 μm for eWLB applications support the bump pitch of less than 40um. Finer line width and spacing are critical for further design flexibility as well as electrical performance improvement. This paper highlights the rapidly moving trend towards eWLB packaging technologies with ultra fine 2/2um line width and line spacing and multi-layer RDL. A package design study, process development and optimization, and mechanical characterization will be discussed as well as test vehicle preparation. JEDEC component level reliability test results will also be presented.

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