scholarly journals Mechanical behavior of flip chip packages under thermal loading

2005 ◽  
Author(s):  
Shoulung Chen ◽  
C.Z. Tsai ◽  
N. Kao ◽  
Enboa Wu
Keyword(s):  
Mechanical Behavior ◽  
Flip Chip ◽  
Thermal Loading

Solder Joint Reliability in Underfilled Flip Chip Package With a Consideration of Chip-Package-Interaction (CPI)

2011 ◽  
Author(s):  
Jae B. Kwak ◽  
Da Yu ◽  
Tung T. Nguyen ◽  
Seungbae Park
Keyword(s):  
Mechanical Behavior ◽  
Flip Chip ◽  
Thermal Loading ◽  
Solder Bump ◽  
Image Correlation ◽  
Specimen Preparation ◽  
Solder Bumps ◽  
Low K ◽  
Underfill Material ◽  
Dic Technique

Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which may compromise the life of flipchip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital Image Correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of a solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. As a specimen preparation for DIC technique, a flip-chip specimen was cross-sectioned before a manual polishing process followed by wet etching method in order to generate natural speckle patterns with high enough contrast on the measuring surface. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young’s modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.

Micro-Mechanical Deformation Analysis of Surface Laminar Circuit in Organic Flip-Chip Package: An Experimental Study

2000 ◽  
Vol 122 (4) ◽  
pp. 294-300 ◽  
Author(s):  
B. Han ◽  
P. Kunthong
Keyword(s):  
Flip Chip ◽  
Thermal Loading ◽  
Region Of Interest ◽  
Deformation Analysis ◽  
High Modulus ◽  
Displacement Fields ◽  
Complex Deformation ◽  
Mechanical Deformations ◽  
Displacement Sensitivity ◽  
Package Reliability

Thermo-mechanical deformations of microstructures in a surface laminar circuit (SLC) substrate are quantified by microscopic moire´ interferometry. Two specimens are analyzed; a bare SLC substrate and a flip chip package assembly. The specimens are subjected to a uniform thermal loading of ΔT=−70°C and the microscopic displacement fields are documented at the identical region of interest. The nano-scale displacement sensitivity and the microscopic spatial resolution obtained from the experiments provide a faithful account of the complex deformation of the surface laminar layer and the embedded microstructures. The displacement fields are analyzed to produce the deformed configuration of the surface laminar layer and the strain distributions in the microstructures. The high modulus of underfill produces a strong coupling between the chip and the surface laminar layer, which produces a DNP-dependent shear deformation of the layer. The effect of the underfill on the deformation of the microstructures is investigated and its implications on the package reliability are discussed. [S1043-7398(00)01304-9]

The mechanical behavior of conductors exposed to short-duration thermal loading

2005 ◽  
Vol 41 (1) ◽  
pp. 256-261 ◽  
Author(s):  
R. Watkins ◽  
K. Ravi-Chandar ◽  
S. Satapathy
Keyword(s):  
Mechanical Behavior ◽  
Short Duration ◽  
Thermal Loading

Interfacial Stress Analysis and Fracture of a Bi-Material Strip With a Heterogeneous Underfill

2003 ◽  
Vol 125 (3) ◽  
pp. 400-413 ◽  
Author(s):  
Ji Eun Park ◽  
Iwona Jasiuk ◽  
Aleksander Zubelewicz
Keyword(s):  
Composite Material ◽  
Stress Intensity ◽  
Polymer Matrix ◽  
Flip Chip ◽  
Thermal Loading ◽  
Interfacial Stress ◽  
J Integral ◽  
Intensity Factors ◽  
Main Components ◽  
Random Particle

Flip chip assemblies used in electronic packaging consist of three main components (layers): chip, underfill, and substrate. In this paper, the flip chip assembly is represented as a bi-material strip consisting of the chip and underfill. Our analysis is focused on delamination along the chip-underfill interface due to thermal loading. The underfill is modeled as a composite material made of a polymer matrix and silica particles. Interfacial stresses are studied for several particle configurations: cases of one, two, or three particles near the interface and 30 different random particle arrangements. Interfacial fracture is investigated by evaluating the J integral and stress intensity factors. Statistics of random particle arrangements in the underfill are also discussed. The interfacial stress and fracture analyses give the same trends.

Failure Prediction of Flip Chip Packages Using Finite Element Technique

2002 ◽  
Author(s):  
Abm Hasan ◽  
H. Mahfuz ◽  
M. Saha ◽  
S. Jeelani
Keyword(s):  
Finite Element ◽  
Flip Chip ◽  
Thermal Loading ◽  
Failure Modes ◽  
Element Model ◽  
Thermally Induced ◽  
Operational Life ◽  
Flip Chip Assembly ◽  
The Individual ◽  
Element Technique

Flip-chip electronic package undergoes thermal loading during its curing process and operational life. Due to the thermal expansion coefficient (CTE) mismatch of various components, the flip-chip assembly experiences various types of thermally induced stresses and strains. Experimental measurement of these stresses and strains is extremely tedious and rigorous due to the physical limitations in the dimensions of the flip-chip assembly. While experiments provide accurate assessment of stresses and strains at certain locations, a parallel finite element (FE) analysis and analytical study can complementarily determine the displacement, strain and stress fields over the entire region of the flip-chip assembly. Such combination of experimental, finite element and analytical studies are ideal to yield a successful stress analysis of the flip-chip assembly under the various loading conditions. In this study, a two-dimensional finite element model of the flip-chip consisting of the silicon chip, underfill, solder ball, copper pad, solder mask and substrate has been developed. Various stress components under thermal loading condition ranging from −40°C to 150°C have been determined using both the finite element and analytical methods. Stresses such as (σ11, σ12, ε12 etc. are extracted and analyzed for the individual components as well as the entire assembly, and the weakest positions of the flip-chip have been discovered. Detailed description of FE modeling is presented and the different failure modes of chip assembly are discussed.

On the Multiscale Finite Element Analysis for Interfacial Fracture in Cu/Low-K Interconnects

2007 ◽  
Author(s):  
Tz-Cheng Chiu ◽  
Huang-Chun Lin
Keyword(s):  
Thin Film ◽  
Fracture Mechanics ◽  
Interface Crack ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Thermal Loading ◽  
Global Analysis ◽  
Crack Problem ◽  
Element Analysis ◽  
Low K

The interface crack problem in integrated circuit devices was considered by using global and local modeling approach. In the global analysis the thin film interconnect was modeled by a homogenized layer with material constants obtained from representative volume element (RVE) analysis. Local analyses were then considered to determine fracture mechanics parameters. It was shown that the multiscale model with RVE approach gives accurate fracture mechanics parameters for an interface crack under either thermal or mechanical loads; while significant error was observed when the thin film layers are ignored in the global analysis. The problem of an interface crack between low-k dielectric and etch-stop thin film in a flip-chip package under thermal loading was also investigated as an application example of the multiscale modeling.

In‐Situ Mapping and Modeling Verification of Thermomechanical Deformation in Underfilled Flip‐Chip Packaging Using Moiré Interferometry

1996 ◽  
Vol 445 ◽  
Author(s):  
Xiang Dai ◽  
Connie Kim ◽  
Ralf Willecke ◽  
Paul S. Ho
Keyword(s):  
Flip Chip ◽  
Thermal Loading ◽  
Deformation Monitoring ◽  
Moiré Interferometry ◽  
Moire Interferometry ◽  
Fringe Analysis ◽  
Element Analysis ◽  
Solder Bumps ◽  
Thermomechanical Deformation

AbstractAn experimental technique of environmental moiré interferometry has been developed for in‐situ monitoring and analysis of thermomechanical deformation of microelectronics packages subjected to thermal loading under a controlled atmosphere. Coupled with fractional fringe analysis and digital image processing, the environmental moiré interferometry technique achieves accurate and realistic deformation monitoring with high sensitivity and excellent spatial resolution. It has been applied to investigate the thermomechanical deformations induced by thermal loading in an underfilled flip‐chip‐on‐board packaging. The effects of temperature change in the range of 102 °C to 22 °C are analyzed for underfill and solder bumps. In addition, shear deformation and shear strains across the solder bumps are determined as a function of temperature. The experimental results are compared with the results of a finite element analysis for modeling verification. Good agreement between the modeling results and experimental measurements has been found in the overall displacement fields. Through this study, the role of underfill in the thermomechanical deformation of the underfilled flip‐chip package is determined.

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