In‐Situ Mapping and Modeling Verification of Thermomechanical Deformation in Underfilled Flip‐Chip Packaging Using Moiré Interferometry

1996 ◽  
Vol 445 ◽  
Author(s):  
Xiang Dai ◽  
Connie Kim ◽  
Ralf Willecke ◽  
Paul S. Ho
Keyword(s):  
Flip Chip ◽  
Thermal Loading ◽  
Deformation Monitoring ◽  
Moiré Interferometry ◽  
Moire Interferometry ◽  
Fringe Analysis ◽  
Element Analysis ◽  
Solder Bumps ◽  
Thermomechanical Deformation

AbstractAn experimental technique of environmental moiré interferometry has been developed for in‐situ monitoring and analysis of thermomechanical deformation of microelectronics packages subjected to thermal loading under a controlled atmosphere. Coupled with fractional fringe analysis and digital image processing, the environmental moiré interferometry technique achieves accurate and realistic deformation monitoring with high sensitivity and excellent spatial resolution. It has been applied to investigate the thermomechanical deformations induced by thermal loading in an underfilled flip‐chip‐on‐board packaging. The effects of temperature change in the range of 102 °C to 22 °C are analyzed for underfill and solder bumps. In addition, shear deformation and shear strains across the solder bumps are determined as a function of temperature. The experimental results are compared with the results of a finite element analysis for modeling verification. Good agreement between the modeling results and experimental measurements has been found in the overall displacement fields. Through this study, the role of underfill in the thermomechanical deformation of the underfilled flip‐chip package is determined.

Creep Behavior of a Flip-Chip Package by Both FEM Modeling and Real Time Moire´ Interferometry

1998 ◽  
Vol 120 (2) ◽  
pp. 179-185 ◽  
Author(s):  
J. Wang ◽  
Z. Qian ◽  
D. Zou ◽  
S. Liu
Keyword(s):  
Finite Element ◽  
Creep Behavior ◽  
Thermal Load ◽  
Flip Chip ◽  
Moiré Interferometry ◽  
Moire Interferometry ◽  
Initial State ◽  
Element Analysis ◽  
The Finite Element Analysis ◽  
Solder Balls

In this paper, the creep behavior of a flip-chip package under a thermal load was investigated by using nonlinear finite element technique coupled with high density laser moire´ interferometry. The real-time moire´ interferometry technique was used to monitor and measure the time-dependent deformation of flip-chip packages during the test, while the finite element method was adapted to analyze the variation of stresses at edges and corners of interfaces with time by considering the viscoelastic properties of the underfill and the viscoplastic behavior of the solder balls. The results show that the creep behavior of the underfill and the solder balls does not have significant effect on the warpage of the flip-chip under the considered thermal load due to their constrained small volume. The variation of the time-dependent deformation in the flip-chip package caused by the creep behavior of the underfill and the solder balls is in the submicro scale. The maximum steady-state U-displacement is only reduced by up to 6.7 percent compared with the maximum initial state U-displacement. Likewise, the maximum steady-state V-displacement is merely reduced by up to 10 percent compared with the maximum initial state V-displacement. The creep behavior slightly weakens the warpage situation of the flip-chip package. However, the modeling results show that the localized stresses at corners and edges of interfaces greatly decrease due to the consideration of viscoelastic properties of the underfill and the viscoplastic properties of the solder balls, and, thereby, effectively preventing interfaces from cracking. In addition, the predicted deformation values of the flip-chip package obtained from the finite element analysis were compared with the test data obtained from the laser moire´ interferometry technique. It is shown that the deformation values of the flip-chip package predicted from the finite element analysis are in a fair agreement with those obtained from the test.

Deformation and Strain Measurement of Flip-Chip Solder Bump Under In-Situ Thermal Loading

2009 ◽  
Author(s):  
Jae B. Kwak ◽  
Dong Gun Lee ◽  
Tung Nguyen ◽  
Seungbae Park
Keyword(s):  
Deformation Behavior ◽  
Flip Chip ◽  
Thermal Loading ◽  
Solder Bump ◽  
Solder Joints ◽  
Image Correlation ◽  
Solder Bumps ◽  
Comparison Results ◽  
Dic Technique

Thermo-mechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital Image Correlation (DIC) technique with optical microscope was adopted to quantify the deformation behavior and strains of a solder bump of flip-chip package subjected to thermal loading. A flip-chip specimen was cross-sectioned after manual polishing process followed by wet etching method in order to generate natural speckle patterns with high enough contrast on the measuring surface for employing DIC technique. The sample was placed in a miniature heating chamber and subjected to in-situ thermal loading from 25 °C to 100°C. During the heating, sequential microscopic images of the cross-sectioned surface of a solder bump were acquired, and the deformation behavior and strain distributions were successfully measured with submicron accuracy by applying DIC technique on the captured images. The computed full-field displacement fields clearly depicted both normal and shear deformation of the solder bump under the thermal loading. In addition, from the strain fields, it was observed that strains were mostly concentrated on the bottom portion of solder bump near the pad connected to substrate. In order to assess the thermo-mechanical strains of the flip-chip interconnections more quantitatively, the average strains of solder joints at different locations were also measured and compared to one another. By doing so, the strain trends of solder bumps were effectively analyzed with respect to the distance to neutral point (DNP). Finally, finite element analysis was conducted by simulating the thermal loading applied in the experiments, and comparison between the simulation and experimental results of displacements and strains was made. The comparison results exhibited satisfactory agreement, which ensured the validity of the experimental data and methodology. This study can further expedite the studies of electronic-package reliability through fatigue and crack failure analysis of the solder joints due to thermal cyclic loading.

On the Multiscale Finite Element Analysis for Interfacial Fracture in Cu/Low-K Interconnects

2007 ◽  
Author(s):  
Tz-Cheng Chiu ◽  
Huang-Chun Lin
Keyword(s):  
Thin Film ◽  
Fracture Mechanics ◽  
Interface Crack ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Thermal Loading ◽  
Global Analysis ◽  
Crack Problem ◽  
Element Analysis ◽  
Low K

The interface crack problem in integrated circuit devices was considered by using global and local modeling approach. In the global analysis the thin film interconnect was modeled by a homogenized layer with material constants obtained from representative volume element (RVE) analysis. Local analyses were then considered to determine fracture mechanics parameters. It was shown that the multiscale model with RVE approach gives accurate fracture mechanics parameters for an interface crack under either thermal or mechanical loads; while significant error was observed when the thin film layers are ignored in the global analysis. The problem of an interface crack between low-k dielectric and etch-stop thin film in a flip-chip package under thermal loading was also investigated as an application example of the multiscale modeling.

Effect of High Glass Transition Temperature on Reliability of Non-Conductive Film (NCF)

2006 ◽  
Vol 326-328 ◽  
pp. 517-520 ◽  
Author(s):  
Jin Hyoung Park ◽  
Chang Kyu Chung ◽  
Kyoung Wook Paik ◽  
Soon Bok Lee
Keyword(s):  
Glass Transition ◽  
Shear Strain ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Moiré Interferometry ◽  
Moire Interferometry ◽  
Effective Parameters ◽  
Conductive Film ◽  
Interferometry Method ◽  
Stress Free State

Among many factors that influence the reliability of a flip-chip assembly using NCF interconnections, the most effective parameters are often the coefficient of thermal expansion (CTE), the modulus (E), and the glass transition temperatures (Tg). Of these factors, the effect of Tg on thermal deformation and device reliability is significant; however, it has not been shown clearly what effect Tg has on the reliability of NCF. The Tg of a conventional NCF material is approximately 110°C. In this study, a new high Tg NCF material that has a 140oC Tg is proposed. The thermal behaviors of the conventional and new NCFs between -40oC to 150oC are observed using an optical method. Twyman-Green interferometry and the moiré interferometry method are used to measure the thermal micro-deformations. The Twyman-Green interferometry measurement technique is applied to verify the stress-free state. The stress-free temperatures of the conventional and new Tg NCF materials are approximately 100oC and 120oC respectively. A shear strain at a part of the NCF chip edge is measured by moiré interferometry. Additionally, a method to accurately measure the residual warpage and shear strain at room temperature is proposed. Through the analysis of the relationship between the warpage and the shear strain, the effect of the high-Tg NCF material on the reliability is studied.

Sign in / Sign up

Export Citation Format

Share Document