Chip integration of Sea of Leads compliant I/O interconnections for the ultimate enabling of chips with low-k interlayer dielectrics
2017 ◽
Vol 3
(12)
◽
pp. 1700116
◽
2001 ◽
pp. 4644-4651
◽
2005 ◽
Vol 28
(3)
◽
pp. 488-494
◽
2000 ◽
Vol 15
(4)
◽
pp. 309-314
◽
Keyword(s):
Keyword(s):
2010 ◽
Vol 11
◽
pp. 85-88
◽