Chip integration of Sea of Leads compliant I/O interconnections for the ultimate enabling of chips with low-k interlayer dielectrics

Author(s):  
M.S. Bakir ◽  
Bing Dang ◽  
R. Emery ◽  
G. Vandentop ◽  
K.P. Martin ◽  
...  
Keyword(s):  
2017 ◽  
Vol 3 (12) ◽  
pp. 1700116 ◽  
Author(s):  
Bradley J. Nordell ◽  
Thuong D. Nguyen ◽  
Anthony N. Caruso ◽  
Sudhaunshu S. Purohit ◽  
Nathan A. Oyler ◽  
...  

2005 ◽  
Vol 28 (3) ◽  
pp. 488-494 ◽  
Author(s):  
M.S. Bakir ◽  
B. Dang ◽  
R. Emery ◽  
G. Vandentop ◽  
P.A. Kohl ◽  
...  

2021 ◽  
Author(s):  
Yudi Feng ◽  
Ke Jin ◽  
Jia Guo ◽  
Changchun Wang

The development of modern microelectronic industry calls for low permittivity interlayer dielectric materials with excellent thermal stabilities, robust mechanical strength and matching processability. Traditionally, it is difficult to fabricate materials...


2005 ◽  
Author(s):  
Nobutoshi Fujii ◽  
Kazuo Kohmura ◽  
Takahiro Nakayama ◽  
Hirofumi Tanaka ◽  
Nobuhiro Hata ◽  
...  

2002 ◽  
Vol 734 ◽  
Author(s):  
Alok Nandini U. Roy ◽  
Zubin P. Patel ◽  
A. Mallikarjunan ◽  
H. Bakhru ◽  
T.-M. Lu

ABSTRACTThin films of Ultra-Low K materials such as Xerogel (K=1.76) and MSQ (K=2.2) were implanted with argon, neon, nitrogen, carbon and helium with 2 × 1015 cm−2 and 1 × 1016 cm−2 dose at energies varying from 20 to 50 keV at room temperature. In this work we showed that the surface hardness of the porous films is improved five times as compared to the as-deposited porous films sacrificing the dielectric constant up to 15% after implantation (e.g., from 1.76 to 2.0). The hardness persists after 450 °C annealing. It is also shown that implantation can prevent the penetration of chemical gases such as CVD precursors in the Ultra-Low K dielectrics during a CVD process.


2001 ◽  
Vol 89 (4) ◽  
pp. 2189-2193 ◽  
Author(s):  
K. Postava ◽  
T. Yamaguchi

2010 ◽  
Vol 11 ◽  
pp. 85-88 ◽  
Author(s):  
Woo Teck Kwon ◽  
J.H. Lee ◽  
Soo Ryong Kim ◽  
H.T. Kim ◽  
Hyung Sun Kim ◽  
...  

In our study, the dielectric properties of SiOC low k thin film derived from polyphenylcarbosilane were investigated as a potential interlayer dielectrics for Cu interconnect technology. A SiOC low k thin film was fabricated onto a n-type silicon wafer by dip coating using 30wt % polyphenylcarbosilane in cyclohexane. Curing of the film was performed in air at 300°C for 2h. The thickness of the film ranges from 1 μm to 1.7 μm. The dielectric constant was determined from the capacitance data obtained from metal/polyphenylcarbosilane/conductive Si MIM capacitors and shows a dielectric constant as low as 3.26 without porosity added. The SiOC low k thin film derived from polyphenylcarbosilane shows promising application as an interlayer dielectrics for Cu interconnect technology.


Sign in / Sign up

Export Citation Format

Share Document