Characterization of interfacial thermal resistance for packaging high-power electronics modules

Author(s):  
S. Haque ◽  
Guo-Quan Lu
Author(s):  
Man Li ◽  
Yanan Yue

The negative influence of substrate on in-plane phonon transport in graphene has been revealed by intensive research, whereas the interaction between phonons couplings across graphene/substrate interface and within graphene is still needed to figure out. In this work, we put forward a two-step Raman method to accomplish interface thermal resistance characterization of graphene/SiO2 and in-plane thermal conductivity measurement of supported graphene by SiO2. In order to calculate the interfacial thermal resistance, the temperature difference between graphene and its substrate was probed using Raman thermometry after the graphene film was uniformly electrically heated. Combing the ITR and the temperature response of graphene to laser heating, the thermal conductivity was computed using the fin heat transfer model. Our results shows that the thermal resistance of free graphene/SiO2 is enormous and the thermal conductivity of the supported graphene is significantly suppressed. The phonons scattering and leakage at the interface are mainly responsible for the reduction of thermal conductivity of graphene on substrate. The morphology change of graphene caused by heating mainly determines the huge interfacial thermal resistance and partly contributes to the suppression of thermal conductivity of graphene. This thermal characterization approach simultaneously realizes the non-contact and non-destructive measurement of interfacial thermal resistance and thermal conductivity of graphene interface materials.


2000 ◽  
Vol 40 (3) ◽  
pp. 465-476 ◽  
Author(s):  
Shatil Haque ◽  
Guo-Quan Lu ◽  
J. Goings ◽  
J. Sigmund

Author(s):  
Peter deBock ◽  
Rinaldo Miorini ◽  
Cathleen Hoel ◽  
Darin Sharar ◽  
Bryan Whalen

Abstract The increasing demand for high power density wide-bandgap power electronics has propelled heat transfer research leading to a constant increase in the thermal performance of cold plates and heat sinks. Most of this research has focused on reducing thermal resistance of the package which can have a detrimental effect on transient thermal performance if thermal capacitance is reduced. In order to provide both a low thermal resistance and a higher thermal capacitance integrated into the package and near the thermal junction, a new cold plate called the Package Integrated Cyclone COoler (PICCO) was developed. GE Research and the US Army Research Lab collaborated to explore and validate the potential of this concept. The PICCO coldplate, which is enabled by 3D printing, establishes a swirling coolant flow field to remove heat. The swirling flow is anticipated to significantly aid in vapor removal from the surface and hence allow for the fluid to provide thermal capacitance through two-phase heat transfer efficiently. This paper describes the experiment design and development for thermal storage and cooling performance characterization of PICCO. The test rig includes a high-pressure capability gear pump moving fluid first through a Coriolis flowmeter and then through PICCO, where the fluid is accelerated in the cyclone and heated by miniaturized ceramic heaters, simulating SiC power electronics. The coolant releases the accumulated enthalpy to a plate-fin heat exchanger that is connected to a chiller. Several absolute and differential pressure transducers and thermocouples monitor the state of FC-72. The experiments will provide empirical transfer functions characterizing the PICCO pressure drop, heat transfer coefficient, critical heat flux and thermal energy storage capability.


2015 ◽  
Vol 106 (11) ◽  
pp. 111906 ◽  
Author(s):  
Huarui Sun ◽  
Roland B. Simon ◽  
James W. Pomeroy ◽  
Daniel Francis ◽  
Firooz Faili ◽  
...  

2013 ◽  
Vol 651 ◽  
pp. 706-709 ◽  
Author(s):  
Zhan Feng Zhao ◽  
Juan Ye

LED performance was significantly improved because of the improvement of encapsulation design and materials properties. The design key points were reviewed in point view of optical, electrical, thermal, and reliability consideration. It was concluded that the packaging design should be simultaneously implemented with the chip design, integrally considering the optics, electrics, thermal, and reliability together. The interfacial thermal resistance and stress from packaging also play critical roles for the optical efficiency and reliability of packaged LED device.


2004 ◽  
Author(s):  
Simon S. Ang ◽  
Paneer Selvam ◽  
Ajay Malshe ◽  
Fred Barlow

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