scholarly journals High speed WDM interconnect using silicon photonics ring modulators and mode-locked laser

Author(s):  
J. Muller ◽  
J. Hauck ◽  
A. Moscoso-Martir ◽  
N. Chimot ◽  
S. Romero-Garcia ◽  
...  
2015 ◽  
Author(s):  
J. Müller ◽  
J. Hauck ◽  
B. Shen ◽  
S. Romero-García ◽  
E. Islamova ◽  
...  

2016 ◽  
Author(s):  
P. De Dobbelaere ◽  
G. Armijo ◽  
J. Balardeta ◽  
B. Chase ◽  
Y. Chi ◽  
...  

2005 ◽  
Vol 13 (6) ◽  
pp. 1916 ◽  
Author(s):  
Alexander Killi ◽  
Jochen D�rring ◽  
Uwe Morgner ◽  
Max J. Lederer ◽  
J�rgen Frei ◽  
...  

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001663-001681
Author(s):  
Miguel Jimarez

We introduce a high-speed 4x25Gbps, MSA-compliant, QSFP transceiver built on a Silicon Photonics platform. The transceiver integrates high sensitivity receivers, CTLE, clock recovery, modulator drivers and BIST on a TSMC 28nm die connected to the photonic die thru a fine pitch (50um) Copper Pillar interface. A wafer-scale approach, Chip on Wafer, CoW, is used to assemble the electronic die and the light source on to the photonic die, so that the full optical path can be tested, at speed, in loopback configuration in wafer form, using a standard ATE solution. This presentation focuses on the CoW assembly development aspects of the transceiver. Wafer probe and bump, die processing services, CoW assembly and Back End of Line, BEOL, Test Services will be presented.


2010 ◽  
Vol 18 (17) ◽  
pp. 18312 ◽  
Author(s):  
A. H. Atabaki ◽  
E. Shah Hosseini ◽  
A. A. Eftekhar ◽  
S. Yegnanarayanan ◽  
A. Adibi
Keyword(s):  

2009 ◽  
Author(s):  
C. W. Holzwarth ◽  
R. Amatya ◽  
M. Araghchini ◽  
J. Birge ◽  
H. Byun ◽  
...  

Nanophotonics ◽  
2014 ◽  
Vol 3 (4-5) ◽  
pp. 205-214 ◽  
Author(s):  
Ari Novack ◽  
Matt Streshinsky ◽  
Ran Ding ◽  
Yang Liu ◽  
Andy Eu-Jin Lim ◽  
...  

AbstractRapid progress has been made in recent years repurposing CMOS fabrication tools to build complex photonic circuits. As the field of silicon photonics becomes more mature, foundry processes will be an essential piece of the ecosystem for eliminating process risk and allowing the community to focus on adding value through clever design. Multi-project wafer runs are a useful tool to promote further development by providing inexpensive, low-risk prototyping opportunities to academic and commercial researchers. Compared to dedicated silicon manufacturing runs, multi-project-wafer runs offer cost reductions of 100× or more. Through OpSIS, we have begun to offer validated device libraries that allow designers to focus on building systems rather than modifying device geometries. The EDA tools that will enable rapid design of such complex systems are under intense development. Progress is also being made in developing practical optical and electronic packaging solutions for the photonic chips, in ways that eliminate or sharply reduce development costs for the user community. This paper will provide a review of the recent developments in silicon photonic foundry offerings with a focus on OpSIS, a multi-project-wafer foundry service offering a silicon photonics platform, including a variety of passive components as well as high-speed modulators and photodetectors, through the Institute of Microelectronics in Singapore.


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