A Scalable Distributed Asynchronous Control Network for High Level Synthesis of Digital Circuits

2011 14th Euromicro Conference on Digital System Design ◽

10.1109/dsd.2011.114 ◽

2011 ◽

Author(s):

Tom van Leeuwen ◽

Rene van Leuken

Keyword(s):

Digital Circuits ◽

High Level Synthesis ◽

Control Network ◽

Asynchronous Control ◽

High Level

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Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2009.2035542 ◽

2010 ◽

Vol 29 (3) ◽

pp. 479-492 ◽

Cited By ~ 13

Author(s):

Chandan Karfa ◽

Dipankar Sarkar ◽

Chittaranjan Mandal

Keyword(s):

Digital Circuits ◽

High Level Synthesis ◽

High Level

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Automatic distributed asynchronous control circuit generation from data flow graph for asynchronous high-level synthesis

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) ◽

10.1109/iscas.2000.856255 ◽

2002 ◽

Author(s):

Euiseok Kim ◽

Jeong-Gun Lee ◽

Dong-Ik Lee

Keyword(s):

Data Flow ◽

Control Circuit ◽

High Level Synthesis ◽

Data Flow Graph ◽

Flow Graph ◽

Asynchronous Control ◽

High Level

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High-level synthesis of digital circuits by finding fixpoints

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC ◽

10.1109/edtc.1994.326892 ◽

2002 ◽

Author(s):

L. Ghatraju ◽

M.H. Abd-El-Barr ◽

C. McCrosky

Keyword(s):

Digital Circuits ◽

High Level Synthesis ◽

High Level

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A genetic algorithm approach to high-level synthesis of digital circuits

International Journal of Systems Science ◽

10.1080/00207729708929412 ◽

1997 ◽

Vol 28 (5) ◽

pp. 517-522

Author(s):

INDRANIL SENGUPTA ◽

NEERAJ BHATIA

Keyword(s):

Genetic Algorithm ◽

Digital Circuits ◽

High Level Synthesis ◽

Genetic Algorithm Approach ◽

High Level

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Dynamically increasing the scope of code motions during the high-level synthesis of digital circuits

IEE Proceedings - Computers and Digital Techniques ◽

10.1049/ip-cdt:20030839 ◽

2003 ◽

Vol 150 (5) ◽

pp. 330 ◽

Cited By ~ 7

Author(s):

S. Gupta ◽

N. Dutt ◽

R. Gupta ◽

A. Nicolau

Keyword(s):

Digital Circuits ◽

High Level Synthesis ◽

High Level

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SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits

10.1007/b117058 ◽

2004 ◽

Cited By ~ 1

Keyword(s):

Digital Circuits ◽

High Level Synthesis ◽

High Level

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High-level synthesis of digital circuits using global scheduling and binding algorithms.

10.22215/etd/1988-09796 ◽

1988 ◽

Cited By ~ 3

Author(s):

Pierre Paulin

Keyword(s):

Digital Circuits ◽

High Level Synthesis ◽

Global Scheduling ◽

High Level

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High-Level Synthesis of Digital Circuits

Advances in Computers - Advances in Computers Volume 37 ◽

10.1016/s0065-2458(08)60406-4 ◽

1993 ◽

pp. 207-283 ◽

Cited By ~ 1

Author(s):

Giovanni De Micheli

Keyword(s):

Digital Circuits ◽

High Level Synthesis ◽

High Level

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High-level synthesis of digital circuits using genetic algorithms

1998 IEEE International Conference on Evolutionary Computation Proceedings. IEEE World Congress on Computational Intelligence (Cat. No.98TH8360) ◽

10.1109/icec.1998.699505 ◽

2002 ◽

Cited By ~ 21

Author(s):

E. Torbey ◽

J. Knight

Keyword(s):

Genetic Algorithms ◽

Digital Circuits ◽

High Level Synthesis ◽

High Level

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Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.137516 ◽

1992 ◽

Vol 11 (6) ◽

pp. 696-718 ◽

Cited By ~ 45

Author(s):

D.C. Ku ◽

G. De Mitcheli

Keyword(s):

Digital Circuits ◽

High Level Synthesis ◽

Timing Constraints ◽

High Level

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