Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits

1992 ◽  
Vol 11 (6) ◽  
pp. 696-718 ◽  
Author(s):  
D.C. Ku ◽  
G. De Mitcheli
Keyword(s):  
Digital Circuits ◽  
High Level Synthesis ◽  
Timing Constraints ◽  
High Level

Bus Optimization for Low Power in High-Level Synthesis

2003 ◽  
Vol 12 (01) ◽  
pp. 1-17
Author(s):  
Sungpack Hong ◽  
Taewhan Kim
Keyword(s):  
Optimal Solution ◽  
Minimum Cost ◽  
Maximum Flow ◽  
High Level Synthesis ◽  
Benchmark Problems ◽  
Timing Constraints ◽  
Power Efficient ◽  
High Level ◽  
The Impact ◽  
Operation Scheduling

Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral level and the RT level of design. This paper addresses the problem of minimizing power dissipated in the switching of the buses in the high-level synthesis of data-dominated behavioral descriptions. Unlike the previous approaches in which the minimization of the power consumed in buses has not been considered until operation scheduling is completed, our approach integrates the bus binding problem into scheduling to exploit the impact of scheduling on the reduction of power dissipated on the buses more fully and effectively. We accomplish this by formulating the problem into a flow problem in a network, and devising an efficient algorithm which iteratively finds the maximum flow of minimum cost solutions in the network. Experimental results on a number of benchmark problems show that given resource and global timing constraints our designs are 19.8% power-efficient over the designs produced by a random-move based solution, and 15.5% power-efficient over the designs by a clock-step based optimal solution.

scholarly journals High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

2011 ◽  
Vol 2011 ◽  
pp. 1-17 ◽  
Author(s):  
John Curreri ◽  
Greg Stitt ◽  
Alan D. George
Keyword(s):  
Timing Analysis ◽  
High Level Synthesis ◽  
Timing Constraints ◽  
Software Developers ◽  
Design Complexity ◽  
Elapsed Time ◽  
Area Overhead ◽  
Limited Support ◽  
Significant Performance ◽  
High Level

Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. Such tools generally rely on inaccurate software simulation or lengthy register-transfer-level simulations, which are unattractive to software developers. In this paper, we introduce HLS techniques that allow application designers to efficiently synthesize commonly used ANSI-C assertions into FPGA circuits, enabling verification and debugging of circuits generated from HLS tools, while executing in the actual FPGA environment. To verify that HLS-generated circuits meet execution timing constraints, we extend the in-circuit assertion support for testing of elapsed time for arbitrary regions of code. Furthermore, we generalize timing assertions to transparently provide hang detection that back annotates hang occurrences to source code. The presented techniques enable software developers to rapidly verify, debug, and analyze timing for FPGA applications, while reducing frequency by less than 3% and increasing FPGA resource utilization by 0.7% or less for several application case studies on the Altera Stratix-II EP2S180 and Stratix-III EP3SE260 using Impulse-C. The presented techniques reduced area overhead by as much as 3x and improved assertion performance by as much as 100% compared to unoptimized in-circuit assertions.

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