Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools ◽

10.1109/dsd.2009.203 ◽

2009 ◽

Cited By ~ 9

Author(s):

Maurizio Palesi ◽

Fabrizio Fazzino ◽

Giuseppe Ascia ◽

Vincenzo Catania

Keyword(s):

Low Power ◽

Networks On Chip ◽

Switched Networks ◽

Data Encoding ◽

On Chip

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Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip

Journal of Computer Science ◽

10.3844/jcssp.2015.552.566 ◽

2015 ◽

Vol 11 (3) ◽

pp. 552-566 ◽

Cited By ~ 1

Author(s):

Maurizio Palesi ◽

Davide Patti ◽

Giuseppe Ascia ◽

Daniela Panno ◽

Vincenzo Catania

Keyword(s):

Low Power ◽

Routing Algorithm ◽

Power Networks ◽

Networks On Chip ◽

Data Encoding ◽

On Chip

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The case for low-power photonic networks on chip

2007 44th ACM/IEEE Design Automation Conference ◽

10.1145/1278480.1278513 ◽

2007 ◽

Cited By ~ 39

Author(s):

Assaf Shacham ◽

Keren Bergman ◽

Luca P. Carloni

Keyword(s):

Low Power ◽

Photonic Networks ◽

Networks On Chip ◽

On Chip

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A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands

Integration ◽

10.1016/j.vlsi.2011.11.010 ◽

2012 ◽

Vol 45 (3) ◽

pp. 271-281 ◽

Cited By ~ 7

Author(s):

Nishit Kapadia ◽

Sudeep Pasricha

Keyword(s):

Low Power ◽

Interconnection Networks ◽

Networks On Chip ◽

On Chip ◽

Low Power Synthesis ◽

Voltage Islands

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Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths

Integration ◽

10.1016/j.vlsi.2014.10.003 ◽

2015 ◽

Vol 50 ◽

pp. 193-204

Author(s):

Mehdi Modarressi ◽

Nasibeh Teimouri ◽

Hamid Sarbazi-azad

Keyword(s):

Networks On Chip ◽

Switched Networks ◽

On Chip

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A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip

2009 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2009.19 ◽

2009 ◽

Cited By ~ 81

Author(s):

Huaxi Gu ◽

Kwai Hung Mo ◽

Jiang Xu ◽

Wei Zhang

Keyword(s):

Low Power ◽

Optical Networks ◽

Low Cost ◽

Multiprocessor Systems ◽

Optical Router ◽

Networks On Chip ◽

Systems On Chip ◽

On Chip

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Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - Lecture Notes in Computer Science ◽

10.1007/978-3-642-17752-1_16 ◽

2011 ◽

pp. 160-169

Author(s):

Alberto Garcia-Ortiz ◽

Leandro S. Indrusiak

Keyword(s):

Low Power ◽

Networks On Chip ◽

On Chip ◽

Theoretical Considerations

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Low-power Networks-on-Chip: Progress and remaining challenges

International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2013.6629279 ◽

2013 ◽

Cited By ~ 6

Author(s):

Mark Buckler ◽

Wayne Burleson ◽

Greg Sadowski

Keyword(s):

Low Power ◽

Power Networks ◽

Networks On Chip ◽

On Chip

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Early performance estimation in wormhole-switched Networks-on-Chip

2008 Canadian Conference on Electrical and Computer Engineering ◽

10.1109/ccece.2008.4564530 ◽

2008 ◽

Author(s):

Victor Dumitriu ◽

Gul N. Khan

Keyword(s):

Performance Estimation ◽

Networks On Chip ◽

Switched Networks ◽

Early Performance ◽

On Chip

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Low power heterogeneous 3D Networks-on-Chip architectures

2011 International Conference on High Performance Computing & Simulation ◽

10.1109/hpcsim.2011.5999871 ◽

2011 ◽

Cited By ~ 9

Author(s):

Michael Opoku Agyeman ◽

Ali Ahmadinia ◽

Alireza Shahrabi

Keyword(s):

Low Power ◽

Networks On Chip ◽

On Chip ◽

3D Networks

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Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06) ◽

10.1109/isvlsi.2006.42 ◽

2006 ◽

Cited By ~ 1

Author(s):

J.C.S. Palma ◽

R.A.L. Reis ◽

L. Soares Indrusiak ◽

A. Garcia Ortiz ◽

M. Glesner ◽

...

Keyword(s):

Power Consumption ◽

Networks On Chip ◽

Data Encoding ◽

On Chip ◽

The Impact

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